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Searched refs:getShiftType (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
543 assert(AArch64_AM::getShiftType(ShiftOpnd) == AArch64_AM::LSL && in getImm8OptLsl()
H A DAArch64InstPrinter.cpp1055 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL && in printShifter()
1058 O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val)) in printShifter()
1702 assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && in printImm8OptLsl()
H A DAArch64AddressingModes.h74 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() function
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedPredicates.td47 let FunctionMapper = "AArch64_AM::getShiftType" in {
H A DAArch64InstrInfo.cpp888 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5; in isFalkorShiftExtFast()
914 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 31); in isFalkorShiftExtFast()
922 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 63); in isFalkorShiftExtFast()
H A DAArch64ISelDAGToDAG.cpp2324 if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSL) { in getUsefulBitsFromOrWithShiftedReg()
2330 } else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) { in getUsefulBitsFromOrWithShiftedReg()