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Searched refs:getSchedModel (Results 1 – 25 of 44) sorted by relevance

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/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/
H A DSchedClassResolutionTest.cpp31 const auto &SM = STI.getSchedModel(); in X86SchedClassResolutionTest()
68 computeIdealizedProcResPressure(STI.getSchedModel(), {{P0Idx, 2}}); in TEST_F()
74 computeIdealizedProcResPressure(STI.getSchedModel(), {{P05Idx, 2}}); in TEST_F()
81 STI.getSchedModel(), {{P05Idx, 2}, {P0156Idx, 2}}); in TEST_F()
90 STI.getSchedModel(), {{P1Idx, 1}, {P05Idx, 1}, {P0156Idx, 2}}); in TEST_F()
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/PowerPC/
H A DAnalysisTest.cpp39 const auto &SM = STI->getSchedModel(); in PPCAnalysisTest()
74 computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUIdx, 2}}); in TEST_F()
80 computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUEIdx, 2}}); in TEST_F()
86 computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUIdx, 1}, {IPAGENIdx, 1}}); in TEST_F()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DSchedClassResolution.cpp53 const auto &SM = STI.getSchedModel(); in getNonRedundantWriteProcRes()
210 SCDesc(STI.getSchedModel().getSchedClassDesc(ResolvedSchedClassId)), in ResolvedSchedClass()
214 STI.getSchedModel(), NonRedundantWriteProcRes)) { in ResolvedSchedClass()
223 const auto &SM = STI.getSchedModel(); in ResolveVariantSchedClassId()
236 const bool WasVariant = SchedClassId && SubtargetInfo.getSchedModel() in resolveSchedClassId()
252 const auto &SchedModel = STI.getSchedModel(); in findProcResIdx()
H A DAnalysis.cpp142 SubtargetInfo_->getSchedModel().getSchedClassDesc(SchedClassId); in printInstructionRowCsv()
386 const auto &SM = SubtargetInfo_->getSchedModel(); in printSchedClassDescHtml()
422 writeEscaped<kEscapeHtml>(OS, SubtargetInfo_->getSchedModel() in printSchedClassDescHtml()
/llvm-project-15.0.7/llvm/tools/llvm-mca/Views/
H A DRegisterFileStatistics.cpp22 const MCSchedModel &SM = STI.getSchedModel(); in RegisterFileStatistics()
121 assert(STI.getSchedModel().hasExtraProcessorInfo() && in printView()
124 STI.getSchedModel().getExtraProcessorInfo(); in printView()
H A DResourcePressureView.cpp27 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in ResourcePressureView()
109 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in printResourcePressurePerIter()
153 printColumnNames(FOS, getSubTargetInfo().getSchedModel()); in printResourcePressurePerInst()
H A DSchedulerStatistics.cpp22 : SM(STI.getSchedModel()), LQResourceID(0), SQResourceID(0), NumIssued(0), in SchedulerStatistics()
25 Usage(STI.getSchedModel().NumProcResourceKinds, {0, 0, 0}) { in SchedulerStatistics()
H A DTimelineView.cpp46 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in onReservedBuffers()
171 getSubTargetInfo().getSchedModel().MicroOpBufferSize); in printWaitTimeEntry()
H A DInstructionInfoView.cpp119 const MCSchedModel &SM = STI.getSchedModel(); in collectData()
/llvm-project-15.0.7/llvm/lib/MCA/
H A DInstrBuilder.cpp36 const MCSchedModel &SM = STI.getSchedModel(); in InstrBuilder()
38 computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks); in InstrBuilder()
45 const MCSchedModel &SM = STI.getSchedModel(); in initializeUsedResources()
297 const MCSchedModel &SM = STI.getSchedModel(); in populateWrites()
543 assert(STI.getSchedModel().hasInstrSchedModel() && in createInstrDescImpl()
549 const MCSchedModel &SM = STI.getSchedModel(); in createInstrDescImpl()
667 *STI.getSchedModel().getSchedClassDesc(D.SchedClassID); in createInstruction()
682 unsigned ProcID = STI.getSchedModel().getProcessorID(); in createInstruction()
H A DContext.cpp34 const MCSchedModel &SM = STI.getSchedModel(); in createDefaultPipeline()
75 const MCSchedModel &SM = STI.getSchedModel(); in createInOrderPipeline()
/llvm-project-15.0.7/llvm/tools/llvm-mca/
H A DPipelinePrinter.cpp52 const MCSchedModel &SM = STI.getSchedModel(); in getJSONSimulationParameters()
82 const MCSchedModel &SM = STI.getSchedModel(); in getJSONTargetInfo()
H A Dllvm-mca.cpp365 if (!STI->getSchedModel().hasInstrSchedModel()) { in main()
371 if (STI->getSchedModel().InstrItineraries) in main()
379 bool IsOutOfOrder = STI->getSchedModel().isOutOfOrder(); in main()
476 const MCSchedModel &SM = STI->getSchedModel(); in main()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetSubtargetInfo.cpp49 return getSchedModel().PostRAScheduler; in enablePostRAScheduler()
H A DVLIWMachineScheduler.cpp272 SchedModel = DAG->getSchedModel(); in initialize()
279 const InstrItineraryData *Itin = DAG->getSchedModel()->getInstrItineraries(); in initialize()
289 Top.ResourceModel = createVLIWResourceModel(STI, DAG->getSchedModel()); in initialize()
290 Bot.ResourceModel = createVLIWResourceModel(STI, DAG->getSchedModel()); in initialize()
/llvm-project-15.0.7/llvm/unittests/tools/llvm-mca/X86/
H A DTestIncrementalMCA.cpp31 auto SV = std::make_unique<SummaryView>(STI->getSchedModel(), MCIs, in TEST_F()
118 auto SV = std::make_unique<SummaryView>(STI->getSchedModel(), MCIs, in TEST_F()
/llvm-project-15.0.7/llvm/lib/MCA/Stages/
H A DInOrderIssueStage.cpp49 : STI(STI), PRF(PRF), RM(STI.getSchedModel()), CB(CB), LSU(LSU), in InOrderIssueStage()
53 return STI.getSchedModel().IssueWidth; in getIssueWidth()
H A DDispatchStage.cpp35 DispatchWidth = Subtarget.getSchedModel().IssueWidth; in DispatchStage()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.cpp133 ? getSchedModel().LoadLatency + 1 in getMaxBuildIntsCost()
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCSchedule.cpp91 const MCSchedModel &SM = STI.getSchedModel(); in getReciprocalThroughput()
/llvm-project-15.0.7/llvm/unittests/tools/llvm-mca/
H A DMCATestBase.cpp103 auto SV = std::make_unique<SummaryView>(STI->getSchedModel(), Insts, in runBaselineMCA()
/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp507 const MCSchedModel &SM = STI.getSchedModel(); in collectWrites()
574 const MCSchedModel &SM = STI.getSchedModel(); in checkRAWHazards()
638 const MCSchedModel &SM = STI.getSchedModel(); in addRegisterRead()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUIGroupLP.cpp261 const TargetSchedModel *TSchedModel = DAGInstrs->getSchedModel(); in apply()
294 const TargetSchedModel *TSchedModel = DAGInstrs->getSchedModel(); in apply()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h163 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; } in getSchedModel() function
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCSubtarget.cpp206 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner; in enableMachinePipeliner()

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