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Searched refs:getReservedRegs (Results 1 – 25 of 68) sorted by relevance

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/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DSnippetRepetitor.cpp43 BitVector getReservedRegs() const override { in getReservedRegs() function in llvm::exegesis::__anon756b83d50111::DuplicateSnippetRepetitor
104 BitVector getReservedRegs() const override { in getReservedRegs() function in llvm::exegesis::__anon756b83d50111::LoopSnippetRepetitor
H A DSnippetRepetitor.h37 virtual BitVector getReservedRegs() const = 0;
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterInfo.cpp24 BitVector SPIRVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { in getReservedRegs() function in SPIRVRegisterInfo
H A DSPIRVRegisterInfo.h26 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.h29 BitVector getReservedRegs(const MachineFunction &MF) const override;
H A DBPFRegisterInfo.cpp37 BitVector BPFRegisterInfo::getReservedRegs(const MachineFunction &MF) const { in getReservedRegs() function in BPFRegisterInfo
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.h30 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.h31 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.h33 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.h32 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVERegisterInfo.h32 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.h29 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.h33 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.h32 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegisterInfo.h36 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCRegisterInfo.h36 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.h39 BitVector getReservedRegs(const MachineFunction &MF) const override;
H A DNVPTXRegisterInfo.cpp108 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const { in getReservedRegs() function in NVPTXRegisterInfo
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.h33 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.h32 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.h57 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.h39 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.h82 BitVector getReservedRegs(const MachineFunction &MF) const override;
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/AMDGPU/
H A Dparse-order-reserved-regs.mir5 # Previously getReservedRegs was called before parsing
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterInfo.h116 BitVector getReservedRegs(const MachineFunction &MF) const override;

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