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/llvm-project-15.0.7/libc/utils/HdrGen/
H A DREADME.md1 # The LLVM libc header generation system
3 LLVM libc uses a header generation scheme to generate public as well as internal
5 which drives this header generation scheme.
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dmcm-obj.ll27 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
50 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
56 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
72 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
78 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
89 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
95 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
111 ; Verify generation of relocations foraccessing variable ti.
130 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
184 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
H A Dmcm-obj-2.ll19 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
38 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
50 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
H A Dtls-pic.ll7 ; Test correct assembly code generation for thread-local storage using
49 ; Test correct assembly code generation for thread-local storage using
/llvm-project-15.0.7/compiler-rt/lib/xray/
H A Dxray_fdr_controller.h47 return B.Data != nullptr && B.Generation == BQ->generation() && in hasSpace()
154 if (B.Generation != BQ->generation()) in recordPreamble()
171 if (B.Generation != BQ->generation()) in recordPreamble()
191 if (B.Generation != BQ->generation()) in rewindRecords()
210 if (B.Generation != BQ->generation()) in rewindRecords()
217 if (B.Generation != BQ->generation()) in rewindRecords()
H A Dxray_buffer_queue.cpp128 Buf.Generation = generation(); in init()
179 Buf.Generation = generation(); in getBuffer()
190 if (Buf.Generation != generation() || LiveBuffers == 0) { in releaseBuffer()
/llvm-project-15.0.7/flang/include/flang/Frontend/
H A DCodeGenOptions.def1 //===--- CodeGenOptions.def - Code generation option database ----- C++ -*-===//
9 // This file defines the code generation options. Users of this file
/llvm-project-15.0.7/mlir/docs/Dialects/
H A DTOSA.md37 order to bound the design of hardware, operator kernels, code generation
50 code generation and hardware development. It therefore incorporates precision
87 the construction of code generation for that operation, or decisions on the
96 the tensors are no longer necessary for code generation.
106 quantization information, to later backend code generation steps.
/llvm-project-15.0.7/mlir/docs/Rationale/
H A DRationaleSimplifiedPolyhedralForm.md228 out after code generation. With the simplified form, transformations have to do
229 parts of code generation inline with their transformation: instead of simply
283 ### Simplicity of code generation
292 come out during code generation. Code generation from ISL shows that it is
303 generation into the transformations themselves - this is sometimes trivial,
305 the code generation algorithms themselves be library functions that
312 more advanced cases like skewing, e.g. for DMA data movement generation.
322 question (see "Cost of code generation").
324 ### Cost of code generation
326 State of the art polyhedral code generation is
[all …]
/llvm-project-15.0.7/polly/test/CodeGen/
H A Dphi_after_error_block_outside_of_scop.ll3 ; Make sure code generation does not break in case an 'error block' is detected
4 ; outside of the scope. In this situation, we should not affect code generation.
H A Dblas_sscal_simplified.ll3 ; Regression test for a bug in the runtime check generation.
6 ; part of the runtime check generation at some point. To be
/llvm-project-15.0.7/llvm/test/ExecutionEngine/RuntimeDyld/ARM/
H A DMachO_ARM_PIC_relocations.s21 # Check stub generation for external symbols by referencing a common symbol, 'baz'.
32 # Check stub generation for internal symbols by referencing 'bar'.
/llvm-project-15.0.7/polly/lib/External/isl/
H A DChangeLog80 - optionally detect min/max expressions during AST generation
108 - deprecate separation_class AST generation option
154 - make code generation output the same on Solaris
161 - make code generation output independent of endianness
168 - add code generation
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-tls-dynamics.ll3 …ne-linux-gnu -stop-after=machineverifier -relocation-model=pic -aarch64-elf-ldtls-generation=1 < %s
5 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -ver…
6 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -fil…
10 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -cod…
12 …-mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -code-model=la…
/llvm-project-15.0.7/polly/
H A DCMakeLists.txt84 option(POLLY_ENABLE_GPGPU_CODEGEN "Enable GPGPU code generation feature" OFF)
87 # Do not require CUDA/OpenCL, as GPU code generation test cases can be run
94 message(WARNING "The LLVM NVPTX target is required for GPU code generation")
99 # Support GPGPU code generation if the library is available.
H A DCREDITS.txt13 D: OpenMP code generation
23 D: GPGPU code generation
/llvm-project-15.0.7/llvm/include/llvm/Frontend/Directive/
H A DDirectiveBase.td28 // Optional prefix used for the generation of the enumerator in the Directive
32 // Optional prefix used for the generation of the enumerator in the Clause
44 // output file of the declaration code generation. Can be left blank.
109 // Prefix before the actual value. Used in the parser generation.
/llvm-project-15.0.7/libc/docs/
H A Dheader_generation.rst9 problems in llvm-libc, we use a header generation mechanism. The mechanism is
16 generation mechanism takes an input file, which has an extension of
19 reading a ``.h.def`` file, the header generation tool does two things:
63 header generation tool when processing a command.
H A Dmechanics_of_public_api.rst4 The build system, in combination with the header generation mechanism,
7 the corresponding ``.h.def`` files. A header generation command ``%%public_api``
/llvm-project-15.0.7/polly/test/ScopInfo/
H A Disl_trip_count_03.ll4 ; in Polly in the old domain generation as ScalarEvolution cannot figure out the
5 ; loop bounds. However, the new domain generation will detect the SCoP.
/llvm-project-15.0.7/openmp/docs/
H A DREADME.txt7 is mostly meant to be processed by the Sphinx documentation generation
43 These .rst files are also included during HTML generation so they are also
/llvm-project-15.0.7/mlir/docs/Tutorials/Toy/
H A D_index.md33 - [Chapter #6](Ch-6.md): Lowering to LLVM and code generation. Here we'll
34 target LLVM IR for code generation, and detail more of the lowering
/llvm-project-15.0.7/llvm/docs/HistoricalNotes/
H A D2001-01-31-UniversalIRIdea.txt12 (some low-level like standard assembly instructions with code generation and
16 needed. Most of the machine-dependent code-generation and optimization
/llvm-project-15.0.7/polly/docs/
H A DUsingPollyWithClang.rst31 Automatic OpenMP code generation
73 Automatic Vector code generation
76 Automatic vector code generation can be enabled by adding -mllvm
166 Disable LLVM-IR generation
171 generation add the option polly-no-codegen.
/llvm-project-15.0.7/llvm/docs/
H A DREADME.txt7 is mostly meant to be processed by the Sphinx documentation generation
42 These .rst files are also included during HTML generation so they are also

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