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Searched refs:ft8 (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Float/
H A Df-conv.s20 # ASM-AND-OBJ: ftintrm.w.s $ft8, $ft8
22 ftintrm.w.s $ft8, $ft8
H A Dd-conv.s45 # ASM-AND-OBJ: ftint.l.d $ft8, $fs0
47 ftint.l.d $ft8, $fs0
65 # ASM-AND-OBJ: ftintrp.l.s $fa0, $ft8
67 ftintrp.l.s $fa0, $ft8
H A Df-move.s64 # ASM-AND-OBJ: movcf2fr $ft8, $fcc0
66 movcf2fr $ft8, $fcc0
H A Df-arith.s28 # ASM-AND-OBJ: fmadd.s $fa3, $ft8, $fa3, $ft7
30 fmadd.s $fa3, $ft8, $fa3, $ft7
H A Dd-arith.s93 # ASM-AND-OBJ: fcopysign.d $ft8, $fs2, $fa6
95 fcopysign.d $ft8, $fs2, $fa6
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drv32d-valid.s13 # CHECK-ASM-AND-OBJ: fadd.s fs10, fs11, ft8
62 # CHECK-ASM-AND-OBJ: fadd.d fs10, fs11, ft8, dyn
105 # CHECK-ASM-AND-OBJ: fle.d a3, ft8, ft9
107 fle.d a3, ft8, ft9
137 # CHECK-ASM-AND-OBJ: fadd.d fs10, fs11, ft8, rmm
H A Drv32f-valid.s57 # CHECK-ASM-AND-OBJ: fadd.s fs10, fs11, ft8, dyn
102 # CHECK-ASM-AND-OBJ: fle.s a3, ft8, ft9
104 fle.s a3, ft8, ft9
139 # CHECK-ASM-AND-OBJ: fadd.s fs10, fs11, ft8, rne
H A Drv32zfh-valid.s57 # CHECK-ASM-AND-OBJ: fadd.h fs10, fs11, ft8, dyn
102 # CHECK-ASM-AND-OBJ: fle.h a3, ft8, ft9
104 fle.h a3, ft8, ft9
139 # CHECK-ASM-AND-OBJ: fadd.h fs10, fs11, ft8, rne
H A Drvd-aliases-valid.s73 # CHECK-INST: fadd.d fs10, fs11, ft8, dyn
74 # CHECK-ALIAS: fadd.d fs10, fs11, ft8{{[[:space:]]}}
H A Drvzfh-aliases-valid.s73 # CHECK-INST: fadd.h fs10, fs11, ft8, dyn
74 # CHECK-ALIAS: fadd.h fs10, fs11, ft8{{[[:space:]]}}
H A Drvf-aliases-valid.s136 # CHECK-INST: fadd.s fs10, fs11, ft8, dyn
137 # CHECK-ALIAS: fadd.s fs10, fs11, ft8{{[[:space:]]}}
H A Dnumeric-reg-names-f.s150 fsqrt.s fa0, ft8
H A Dnumeric-reg-names-d.s150 fsqrt.d fa0, ft8
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dmangle.cpp225 template<typename T> typename __enable_if<(__is_scalar_type<T>::__value), void>::__type ft8() { } in ft8() function
227 template void ft8<int>();
229 template void ft8<void*>();
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dfastcc-float.ll34 ; CHECK-NEXT: flw ft8, 96(sp)
H A Dinterrupt-attr.ll128 ; CHECK-RV32-F-NEXT: fsw ft8, 60(sp) # 4-byte Folded Spill
177 ; CHECK-RV32-F-NEXT: flw ft8, 60(sp) # 4-byte Folded Reload
231 ; CHECK-RV32-FD-NEXT: fsd ft8, 120(sp) # 8-byte Folded Spill
280 ; CHECK-RV32-FD-NEXT: fld ft8, 120(sp) # 8-byte Folded Reload
373 ; CHECK-RV64-F-NEXT: fsw ft8, 60(sp) # 4-byte Folded Spill
422 ; CHECK-RV64-F-NEXT: flw ft8, 60(sp) # 4-byte Folded Reload
476 ; CHECK-RV64-FD-NEXT: fsd ft8, 120(sp) # 8-byte Folded Spill
630 ; CHECK-RV32-F-NEXT: fsw ft8, 72(sp) # 4-byte Folded Spill
681 ; CHECK-RV32-F-NEXT: flw ft8, 72(sp) # 4-byte Folded Reload
884 ; CHECK-RV64-F-NEXT: fsw ft8, 68(sp) # 4-byte Folded Spill
[all …]
H A Dcallee-saved-fpr32s.ll44 ; ILP32-NEXT: flw ft8, 64(a1)
75 ; ILP32-NEXT: fsw ft8, 64(a1)
114 ; LP64-NEXT: flw ft8, 64(a1)
145 ; LP64-NEXT: fsw ft8, 64(a1)
197 ; ILP32F-NEXT: flw ft8, 64(a1)
228 ; ILP32F-NEXT: fsw ft8, 64(a1)
293 ; LP64F-NEXT: flw ft8, 64(a1)
324 ; LP64F-NEXT: fsw ft8, 64(a1)
389 ; ILP32D-NEXT: flw ft8, 64(a1)
485 ; LP64D-NEXT: flw ft8, 64(a1)
[all …]
H A Dinline-asm-f-abi-names.ll1354 ; RV32IF-NEXT: fmv.s ft8, fa0
1356 ; RV32IF-NEXT: fcvt.w.s a0, ft8
1362 ; RV64IF-NEXT: fmv.s ft8, fa0
1364 ; RV64IF-NEXT: fcvt.w.s a0, ft8
1374 ; RV32IF-NEXT: fmv.s ft8, fa0
1376 ; RV32IF-NEXT: fcvt.w.s a0, ft8
1382 ; RV64IF-NEXT: fmv.s ft8, fa0
1384 ; RV64IF-NEXT: fcvt.w.s a0, ft8
1387 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft8}"(float %a)
H A Dinline-asm-d-abi-names.ll1354 ; RV32IFD-NEXT: fmv.d ft8, fa0
1356 ; RV32IFD-NEXT: fcvt.w.d a0, ft8
1362 ; RV64IFD-NEXT: fmv.d ft8, fa0
1364 ; RV64IFD-NEXT: fcvt.w.d a0, ft8
1374 ; RV32IFD-NEXT: fmv.d ft8, fa0
1376 ; RV32IFD-NEXT: fcvt.w.d a0, ft8
1382 ; RV64IFD-NEXT: fmv.d ft8, fa0
1384 ; RV64IFD-NEXT: fcvt.w.d a0, ft8
1387 %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft8}"(double %a)
H A Dcallee-saved-fpr64s.ll40 ; ILP32-NEXT: fld ft8, 128(a1)
71 ; ILP32-NEXT: fsd ft8, 128(a1)
110 ; LP64-NEXT: fld ft8, 128(a1)
141 ; LP64-NEXT: fsd ft8, 128(a1)
193 ; ILP32D-NEXT: fld ft8, 128(a1)
224 ; ILP32D-NEXT: fsd ft8, 128(a1)
289 ; LP64D-NEXT: fld ft8, 128(a1)
320 ; LP64D-NEXT: fsd ft8, 128(a1)
H A Dinterrupt-attr-nocall.ll448 ; CHECK-RV32IF-NEXT: fsw ft8, 60(sp) # 4-byte Folded Spill
506 ; CHECK-RV32IF-NEXT: flw ft8, 60(sp) # 4-byte Folded Reload
641 ; CHECK-RV32IF-NEXT: fsw ft8, 72(sp) # 4-byte Folded Spill
701 ; CHECK-RV32IF-NEXT: flw ft8, 72(sp) # 4-byte Folded Reload
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td119 def F16 : LoongArchReg32<16,"f16", ["ft8"]>, DwarfRegNum<[48]>;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td210 def F28_H : RISCVReg16<28,"f28", ["ft8"]>, DwarfRegNum<[60]>;