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Searched refs:ft7 (Results 1 – 24 of 24) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Float/
H A Df-arith.s12 # ASM-AND-OBJ: fadd.s $fs5, $ft7, $fs1
14 fadd.s $fs5, $ft7, $fs1
28 # ASM-AND-OBJ: fmadd.s $fa3, $ft8, $fa3, $ft7
30 fmadd.s $fa3, $ft8, $fa3, $ft7
56 # ASM-AND-OBJ: fmina.s $ft7, $ft10, $fa1
58 fmina.s $ft7, $ft10, $fa1
H A Dd-arith.s13 # ASM-AND-OBJ: fadd.s $fs5, $ft7, $fs1
15 fadd.s $fs5, $ft7, $fs1
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drv32d-valid.s39 # CHECK-ASM-AND-OBJ: fsd ft7, -2048(s5)
74 # CHECK-ASM-AND-OBJ: fsqrt.d ft6, ft7, dyn
76 fsqrt.d ft6, ft7, dyn
150 # CHECK-ASM-AND-OBJ: fsqrt.d ft6, ft7, rdn
152 fsqrt.d ft6, ft7, rdn
H A Drv32f-valid.s34 # CHECK-ASM-AND-OBJ: fsw ft7, -2048(s5)
69 # CHECK-ASM-AND-OBJ: fsqrt.s ft6, ft7, dyn
71 fsqrt.s ft6, ft7, dyn
152 # CHECK-ASM-AND-OBJ: fsqrt.s ft6, ft7, rmm
154 fsqrt.s ft6, ft7, rmm
H A Drv32zfh-valid.s34 # CHECK-ASM-AND-OBJ: fsh ft7, -2048(s5)
69 # CHECK-ASM-AND-OBJ: fsqrt.h ft6, ft7, dyn
71 fsqrt.h ft6, ft7, dyn
152 # CHECK-ASM-AND-OBJ: fsqrt.h ft6, ft7, rmm
154 fsqrt.h ft6, ft7, rmm
H A Drvd-aliases-valid.s85 # CHECK-INST: fsqrt.d ft6, ft7, dyn
86 # CHECK-ALIAS: fsqrt.d ft6, ft7{{[[:space:]]}}
87 fsqrt.d ft6, ft7
H A Drv64f-valid.s37 # CHECK-ASM-AND-OBJ: fcvt.s.lu ft7, a7, rup
39 fcvt.s.lu ft7, a7, rup
H A Drv64zfh-valid.s37 # CHECK-ASM-AND-OBJ: fcvt.h.lu ft7, a7, rup
39 fcvt.h.lu ft7, a7, rup
H A Drvzfh-aliases-valid.s85 # CHECK-INST: fsqrt.h ft6, ft7, dyn
86 # CHECK-ALIAS: fsqrt.h ft6, ft7{{[[:space:]]}}
87 fsqrt.h ft6, ft7
H A Drvf-aliases-valid.s148 # CHECK-INST: fsqrt.s ft6, ft7, dyn
149 # CHECK-ALIAS: fsqrt.s ft6, ft7{{[[:space:]]}}
150 fsqrt.s ft6, ft7
H A Drv32zfhmin-valid.s34 # CHECK-ASM-AND-OBJ: fsh ft7, -2048(s5)
H A Dnumeric-reg-names-f.s45 fsqrt.s fa0, ft7
H A Dnumeric-reg-names-d.s45 fsqrt.d fa0, ft7
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dcalling-conv-vector-float.ll39 ; RV64-NEXT: flw ft7, 0(sp)
43 ; RV64-NEXT: fadd.s ft0, ft0, ft7
H A Dfastcc-float.ll33 ; CHECK-NEXT: flw ft7, 92(sp)
H A Dinterrupt-attr.ll119 ; CHECK-RV32-F-NEXT: fsw ft7, 96(sp) # 4-byte Folded Spill
168 ; CHECK-RV32-F-NEXT: flw ft7, 96(sp) # 4-byte Folded Reload
222 ; CHECK-RV32-FD-NEXT: fsd ft7, 192(sp) # 8-byte Folded Spill
271 ; CHECK-RV32-FD-NEXT: fld ft7, 192(sp) # 8-byte Folded Reload
364 ; CHECK-RV64-F-NEXT: fsw ft7, 96(sp) # 4-byte Folded Spill
413 ; CHECK-RV64-F-NEXT: flw ft7, 96(sp) # 4-byte Folded Reload
467 ; CHECK-RV64-FD-NEXT: fsd ft7, 192(sp) # 8-byte Folded Spill
621 ; CHECK-RV32-F-NEXT: fsw ft7, 108(sp) # 4-byte Folded Spill
672 ; CHECK-RV32-F-NEXT: flw ft7, 108(sp) # 4-byte Folded Reload
727 ; CHECK-RV32-FD-NEXT: fsd ft7, 200(sp) # 8-byte Folded Spill
[all …]
H A Dcallee-saved-fpr32s.ll35 ; ILP32-NEXT: flw ft7, 28(a1)
84 ; ILP32-NEXT: fsw ft7, 28(a1)
105 ; LP64-NEXT: flw ft7, 28(a1)
154 ; LP64-NEXT: fsw ft7, 28(a1)
188 ; ILP32F-NEXT: flw ft7, 28(a1)
237 ; ILP32F-NEXT: fsw ft7, 28(a1)
284 ; LP64F-NEXT: flw ft7, 28(a1)
333 ; LP64F-NEXT: fsw ft7, 28(a1)
380 ; ILP32D-NEXT: flw ft7, 28(a1)
476 ; LP64D-NEXT: flw ft7, 28(a1)
[all …]
H A Dinline-asm-f-abi-names.ll301 ; RV32IF-NEXT: fmv.s ft7, fa0
303 ; RV32IF-NEXT: fcvt.w.s a0, ft7
309 ; RV64IF-NEXT: fmv.s ft7, fa0
311 ; RV64IF-NEXT: fcvt.w.s a0, ft7
321 ; RV32IF-NEXT: fmv.s ft7, fa0
323 ; RV32IF-NEXT: fcvt.w.s a0, ft7
329 ; RV64IF-NEXT: fmv.s ft7, fa0
331 ; RV64IF-NEXT: fcvt.w.s a0, ft7
334 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft7}"(float %a)
H A Dinline-asm-d-abi-names.ll301 ; RV32IFD-NEXT: fmv.d ft7, fa0
303 ; RV32IFD-NEXT: fcvt.w.d a0, ft7
309 ; RV64IFD-NEXT: fmv.d ft7, fa0
311 ; RV64IFD-NEXT: fcvt.w.d a0, ft7
321 ; RV32IFD-NEXT: fmv.d ft7, fa0
323 ; RV32IFD-NEXT: fcvt.w.d a0, ft7
329 ; RV64IFD-NEXT: fmv.d ft7, fa0
331 ; RV64IFD-NEXT: fcvt.w.d a0, ft7
334 %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft7}"(double %a)
H A Dcallee-saved-fpr64s.ll31 ; ILP32-NEXT: fld ft7, 56(a1)
80 ; ILP32-NEXT: fsd ft7, 56(a1)
101 ; LP64-NEXT: fld ft7, 56(a1)
150 ; LP64-NEXT: fsd ft7, 56(a1)
184 ; ILP32D-NEXT: fld ft7, 56(a1)
233 ; ILP32D-NEXT: fsd ft7, 56(a1)
280 ; LP64D-NEXT: fld ft7, 56(a1)
329 ; LP64D-NEXT: fsd ft7, 56(a1)
H A Dinterrupt-attr-nocall.ll439 ; CHECK-RV32IF-NEXT: fsw ft7, 96(sp) # 4-byte Folded Spill
497 ; CHECK-RV32IF-NEXT: flw ft7, 96(sp) # 4-byte Folded Reload
632 ; CHECK-RV32IF-NEXT: fsw ft7, 108(sp) # 4-byte Folded Spill
692 ; CHECK-RV32IF-NEXT: flw ft7, 108(sp) # 4-byte Folded Reload
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dmangle.cpp194 template<typename T> typename __enable_if<__is_scalar_type<T>::__value, void>::__type ft7() { } in ft7() function
197 template void ft7<int>();
199 template void ft7<void*>();
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td118 def F15 : LoongArchReg32<15,"f15", ["ft7"]>, DwarfRegNum<[47]>;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td189 def F7_H : RISCVReg16<7, "f7", ["ft7"]>, DwarfRegNum<[39]>;