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/llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Float/
H A Df-arith.s16 # ASM-AND-OBJ: fsub.s $ft6, $fa6, $fs7
18 fsub.s $ft6, $fa6, $fs7
48 # ASM-AND-OBJ: fmin.s $ft6, $ft2, $ft11
50 fmin.s $ft6, $ft2, $ft11
H A Df-conv.s24 # ASM-AND-OBJ: ftintrp.w.s $ft6, $fs7
26 ftintrp.w.s $ft6, $fs7
H A Dd-arith.s85 # ASM-AND-OBJ: fscaleb.d $ft4, $ft6, $fs2
87 fscaleb.d $ft4, $ft6, $fs2
H A Dd-conv.s37 # ASM-AND-OBJ: ftint.w.d $fa3, $ft6
39 ftint.w.d $fa3, $ft6
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drvd-aliases-valid.s43 # CHECK-INST: flt.d tp, ft6, ft5
44 # CHECK-ALIAS: flt.d tp, ft6, ft5
85 # CHECK-INST: fsqrt.d ft6, ft7, dyn
86 # CHECK-ALIAS: fsqrt.d ft6, ft7{{[[:space:]]}}
87 fsqrt.d ft6, ft7
H A Drvzfh-aliases-valid.s36 # CHECK-INST: flt.h tp, ft6, ft5
37 # CHECK-ALIAS: flt.h tp, ft6, ft5
85 # CHECK-INST: fsqrt.h ft6, ft7, dyn
86 # CHECK-ALIAS: fsqrt.h ft6, ft7{{[[:space:]]}}
87 fsqrt.h ft6, ft7
H A Drvf-aliases-valid.s43 # CHECK-INST: flt.s tp, ft6, ft5
44 # CHECK-ALIAS: flt.s tp, ft6, ft5
148 # CHECK-INST: fsqrt.s ft6, ft7, dyn
149 # CHECK-ALIAS: fsqrt.s ft6, ft7{{[[:space:]]}}
150 fsqrt.s ft6, ft7
H A Drv32d-valid.s36 # CHECK-ASM-AND-OBJ: fsd ft6, 2047(s4)
74 # CHECK-ASM-AND-OBJ: fsqrt.d ft6, ft7, dyn
76 fsqrt.d ft6, ft7, dyn
150 # CHECK-ASM-AND-OBJ: fsqrt.d ft6, ft7, rdn
152 fsqrt.d ft6, ft7, rdn
H A Drv32f-valid.s31 # CHECK-ASM-AND-OBJ: fsw ft6, 2047(s4)
69 # CHECK-ASM-AND-OBJ: fsqrt.s ft6, ft7, dyn
71 fsqrt.s ft6, ft7, dyn
152 # CHECK-ASM-AND-OBJ: fsqrt.s ft6, ft7, rmm
154 fsqrt.s ft6, ft7, rmm
H A Drv32zfh-valid.s31 # CHECK-ASM-AND-OBJ: fsh ft6, 2047(s4)
69 # CHECK-ASM-AND-OBJ: fsqrt.h ft6, ft7, dyn
71 fsqrt.h ft6, ft7, dyn
152 # CHECK-ASM-AND-OBJ: fsqrt.h ft6, ft7, rmm
154 fsqrt.h ft6, ft7, rmm
H A Drv64f-valid.s34 # CHECK-ASM-AND-OBJ: fcvt.s.l ft6, a6, rdn
36 fcvt.s.l ft6, a6, rdn
H A Drv64zfh-valid.s34 # CHECK-ASM-AND-OBJ: fcvt.h.l ft6, a6, rdn
36 fcvt.h.l ft6, a6, rdn
H A Drv32zfhmin-valid.s31 # CHECK-ASM-AND-OBJ: fsh ft6, 2047(s4)
H A Dnumeric-reg-names-f.s40 fsqrt.s fa0, ft6
H A Dnumeric-reg-names-d.s40 fsqrt.d fa0, ft6
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dcalling-conv-vector-float.ll38 ; RV64-NEXT: fmv.w.x ft6, a1
40 ; RV64-NEXT: fadd.s ft5, ft6, ft5
H A Dfastcc-float.ll32 ; CHECK-NEXT: flw ft6, 88(sp)
H A Dinterrupt-attr.ll118 ; CHECK-RV32-F-NEXT: fsw ft6, 100(sp) # 4-byte Folded Spill
167 ; CHECK-RV32-F-NEXT: flw ft6, 100(sp) # 4-byte Folded Reload
221 ; CHECK-RV32-FD-NEXT: fsd ft6, 200(sp) # 8-byte Folded Spill
270 ; CHECK-RV32-FD-NEXT: fld ft6, 200(sp) # 8-byte Folded Reload
363 ; CHECK-RV64-F-NEXT: fsw ft6, 100(sp) # 4-byte Folded Spill
412 ; CHECK-RV64-F-NEXT: flw ft6, 100(sp) # 4-byte Folded Reload
466 ; CHECK-RV64-FD-NEXT: fsd ft6, 200(sp) # 8-byte Folded Spill
620 ; CHECK-RV32-F-NEXT: fsw ft6, 112(sp) # 4-byte Folded Spill
671 ; CHECK-RV32-F-NEXT: flw ft6, 112(sp) # 4-byte Folded Reload
726 ; CHECK-RV32-FD-NEXT: fsd ft6, 208(sp) # 8-byte Folded Spill
[all …]
H A Dcallee-saved-fpr32s.ll34 ; ILP32-NEXT: flw ft6, 24(a1)
85 ; ILP32-NEXT: fsw ft6, 24(a1)
104 ; LP64-NEXT: flw ft6, 24(a1)
155 ; LP64-NEXT: fsw ft6, 24(a1)
187 ; ILP32F-NEXT: flw ft6, 24(a1)
238 ; ILP32F-NEXT: fsw ft6, 24(a1)
283 ; LP64F-NEXT: flw ft6, 24(a1)
334 ; LP64F-NEXT: fsw ft6, 24(a1)
379 ; ILP32D-NEXT: flw ft6, 24(a1)
475 ; LP64D-NEXT: flw ft6, 24(a1)
[all …]
H A Dinline-asm-f-abi-names.ll261 ; RV32IF-NEXT: fmv.s ft6, fa0
263 ; RV32IF-NEXT: fcvt.w.s a0, ft6
269 ; RV64IF-NEXT: fmv.s ft6, fa0
271 ; RV64IF-NEXT: fcvt.w.s a0, ft6
281 ; RV32IF-NEXT: fmv.s ft6, fa0
283 ; RV32IF-NEXT: fcvt.w.s a0, ft6
289 ; RV64IF-NEXT: fmv.s ft6, fa0
291 ; RV64IF-NEXT: fcvt.w.s a0, ft6
294 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft6}"(float %a)
H A Dinline-asm-d-abi-names.ll261 ; RV32IFD-NEXT: fmv.d ft6, fa0
263 ; RV32IFD-NEXT: fcvt.w.d a0, ft6
269 ; RV64IFD-NEXT: fmv.d ft6, fa0
271 ; RV64IFD-NEXT: fcvt.w.d a0, ft6
281 ; RV32IFD-NEXT: fmv.d ft6, fa0
283 ; RV32IFD-NEXT: fcvt.w.d a0, ft6
289 ; RV64IFD-NEXT: fmv.d ft6, fa0
291 ; RV64IFD-NEXT: fcvt.w.d a0, ft6
294 %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft6}"(double %a)
H A Dcallee-saved-fpr64s.ll30 ; ILP32-NEXT: fld ft6, 48(a1)
81 ; ILP32-NEXT: fsd ft6, 48(a1)
100 ; LP64-NEXT: fld ft6, 48(a1)
151 ; LP64-NEXT: fsd ft6, 48(a1)
183 ; ILP32D-NEXT: fld ft6, 48(a1)
234 ; ILP32D-NEXT: fsd ft6, 48(a1)
279 ; LP64D-NEXT: fld ft6, 48(a1)
330 ; LP64D-NEXT: fsd ft6, 48(a1)
H A Dinterrupt-attr-nocall.ll438 ; CHECK-RV32IF-NEXT: fsw ft6, 100(sp) # 4-byte Folded Spill
496 ; CHECK-RV32IF-NEXT: flw ft6, 100(sp) # 4-byte Folded Reload
631 ; CHECK-RV32IF-NEXT: fsw ft6, 112(sp) # 4-byte Folded Spill
691 ; CHECK-RV32IF-NEXT: flw ft6, 112(sp) # 4-byte Folded Reload
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dmangle.cpp178 template <typename T> typename T::U ft6(const T&) { return 0; } in ft6() function
181 template int ft6<S>(const S&);
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td117 def F14 : LoongArchReg32<14,"f14", ["ft6"]>, DwarfRegNum<[46]>;

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