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/llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Float/
H A Dd-arith.s17 # ASM-AND-OBJ: fadd.d $fs1, $fa7, $ft5
19 fadd.d $fs1, $fa7, $ft5
41 # ASM-AND-OBJ: fnmadd.d $fs1, $ft5, $ft11, $fs6
43 fnmadd.d $fs1, $ft5, $ft11, $fs6
49 # ASM-AND-OBJ: fmax.d $ft3, $fs2, $ft5
51 fmax.d $ft3, $fs2, $ft5
53 # ASM-AND-OBJ: fmin.d $fa1, $ft5, $fs3
55 fmin.d $fa1, $ft5, $fs3
57 # ASM-AND-OBJ: fmaxa.d $fs0, $ft5, $fa4
59 fmaxa.d $fs0, $ft5, $fa4
H A Df-bound-check.s24 # ASM-AND-OBJ: fstle.s $ft5, $t1, $a3
26 fstle.s $ft5, $t1, $a3
H A Dd-bound-check.s25 # ASM-AND-OBJ: fstgt.d $ft5, $a7, $s3
27 fstgt.d $ft5, $a7, $s3
H A Dd-move.s13 # ASM-AND-OBJ: fmov.s $ft5, $ft15
15 fmov.s $ft5, $ft15
H A Df-conv.s16 # ASM-AND-OBJ: ftint.w.s $ft13, $ft5
18 ftint.w.s $ft13, $ft5
H A Df-move.s12 # ASM-AND-OBJ: fmov.s $ft5, $ft15
14 fmov.s $ft5, $ft15
H A Df-arith.s88 # ASM-AND-OBJ: fcopysign.s $ft5, $fs0, $ft15
90 fcopysign.s $ft5, $fs0, $ft15
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dcalling-conv-vector-float.ll37 ; RV64-NEXT: fmv.w.x ft5, a5
40 ; RV64-NEXT: fadd.s ft5, ft6, ft5
47 ; RV64-NEXT: fsw ft5, 0(a0)
H A Dfastcc-float.ll31 ; CHECK-NEXT: flw ft5, 84(sp)
H A Dinterrupt-attr.ll117 ; CHECK-RV32-F-NEXT: fsw ft5, 104(sp) # 4-byte Folded Spill
166 ; CHECK-RV32-F-NEXT: flw ft5, 104(sp) # 4-byte Folded Reload
220 ; CHECK-RV32-FD-NEXT: fsd ft5, 208(sp) # 8-byte Folded Spill
269 ; CHECK-RV32-FD-NEXT: fld ft5, 208(sp) # 8-byte Folded Reload
362 ; CHECK-RV64-F-NEXT: fsw ft5, 104(sp) # 4-byte Folded Spill
411 ; CHECK-RV64-F-NEXT: flw ft5, 104(sp) # 4-byte Folded Reload
465 ; CHECK-RV64-FD-NEXT: fsd ft5, 208(sp) # 8-byte Folded Spill
619 ; CHECK-RV32-F-NEXT: fsw ft5, 116(sp) # 4-byte Folded Spill
670 ; CHECK-RV32-F-NEXT: flw ft5, 116(sp) # 4-byte Folded Reload
725 ; CHECK-RV32-FD-NEXT: fsd ft5, 216(sp) # 8-byte Folded Spill
[all …]
H A Dcallee-saved-fpr32s.ll33 ; ILP32-NEXT: flw ft5, 20(a1)
86 ; ILP32-NEXT: fsw ft5, 20(a1)
103 ; LP64-NEXT: flw ft5, 20(a1)
156 ; LP64-NEXT: fsw ft5, 20(a1)
186 ; ILP32F-NEXT: flw ft5, 20(a1)
239 ; ILP32F-NEXT: fsw ft5, 20(a1)
282 ; LP64F-NEXT: flw ft5, 20(a1)
335 ; LP64F-NEXT: fsw ft5, 20(a1)
378 ; ILP32D-NEXT: flw ft5, 20(a1)
474 ; LP64D-NEXT: flw ft5, 20(a1)
[all …]
H A Dinline-asm-f-abi-names.ll221 ; RV32IF-NEXT: fmv.s ft5, fa0
223 ; RV32IF-NEXT: fcvt.w.s a0, ft5
229 ; RV64IF-NEXT: fmv.s ft5, fa0
231 ; RV64IF-NEXT: fcvt.w.s a0, ft5
241 ; RV32IF-NEXT: fmv.s ft5, fa0
243 ; RV32IF-NEXT: fcvt.w.s a0, ft5
249 ; RV64IF-NEXT: fmv.s ft5, fa0
251 ; RV64IF-NEXT: fcvt.w.s a0, ft5
254 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft5}"(float %a)
H A Dinline-asm-d-abi-names.ll221 ; RV32IFD-NEXT: fmv.d ft5, fa0
223 ; RV32IFD-NEXT: fcvt.w.d a0, ft5
229 ; RV64IFD-NEXT: fmv.d ft5, fa0
231 ; RV64IFD-NEXT: fcvt.w.d a0, ft5
241 ; RV32IFD-NEXT: fmv.d ft5, fa0
243 ; RV32IFD-NEXT: fcvt.w.d a0, ft5
249 ; RV64IFD-NEXT: fmv.d ft5, fa0
251 ; RV64IFD-NEXT: fcvt.w.d a0, ft5
254 %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft5}"(double %a)
H A Dcallee-saved-fpr64s.ll29 ; ILP32-NEXT: fld ft5, 40(a1)
82 ; ILP32-NEXT: fsd ft5, 40(a1)
99 ; LP64-NEXT: fld ft5, 40(a1)
152 ; LP64-NEXT: fsd ft5, 40(a1)
182 ; ILP32D-NEXT: fld ft5, 40(a1)
235 ; ILP32D-NEXT: fsd ft5, 40(a1)
278 ; LP64D-NEXT: fld ft5, 40(a1)
331 ; LP64D-NEXT: fsd ft5, 40(a1)
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drvd-aliases-valid.s43 # CHECK-INST: flt.d tp, ft6, ft5
44 # CHECK-ALIAS: flt.d tp, ft6, ft5
82 # CHECK-INST: fdiv.d ft3, ft4, ft5, dyn
83 # CHECK-ALIAS: fdiv.d ft3, ft4, ft5{{[[:space:]]}}
84 fdiv.d ft3, ft4, ft5
H A Drvzfh-aliases-valid.s36 # CHECK-INST: flt.h tp, ft6, ft5
37 # CHECK-ALIAS: flt.h tp, ft6, ft5
82 # CHECK-INST: fdiv.h ft3, ft4, ft5, dyn
83 # CHECK-ALIAS: fdiv.h ft3, ft4, ft5{{[[:space:]]}}
84 fdiv.h ft3, ft4, ft5
H A Drvf-aliases-valid.s43 # CHECK-INST: flt.s tp, ft6, ft5
44 # CHECK-ALIAS: flt.s tp, ft6, ft5
145 # CHECK-INST: fdiv.s ft3, ft4, ft5, dyn
146 # CHECK-ALIAS: fdiv.s ft3, ft4, ft5{{[[:space:]]}}
147 fdiv.s ft3, ft4, ft5
H A Drv32d-valid.s32 # CHECK-ASM-AND-OBJ: fld ft5, 0(s3)
71 # CHECK-ASM-AND-OBJ: fdiv.d ft3, ft4, ft5, dyn
73 fdiv.d ft3, ft4, ft5, dyn
146 # CHECK-ASM-AND-OBJ: fdiv.d ft3, ft4, ft5, rtz
148 fdiv.d ft3, ft4, ft5, rtz
H A Drv32f-valid.s27 # CHECK-ASM-AND-OBJ: flw ft5, 0(s3)
66 # CHECK-ASM-AND-OBJ: fdiv.s ft3, ft4, ft5, dyn
68 fdiv.s ft3, ft4, ft5, dyn
148 # CHECK-ASM-AND-OBJ: fdiv.s ft3, ft4, ft5, rup
150 fdiv.s ft3, ft4, ft5, rup
H A Drv32zfh-valid.s27 # CHECK-ASM-AND-OBJ: flh ft5, 0(s3)
66 # CHECK-ASM-AND-OBJ: fdiv.h ft3, ft4, ft5, dyn
68 fdiv.h ft3, ft4, ft5, dyn
148 # CHECK-ASM-AND-OBJ: fdiv.h ft3, ft4, ft5, rup
150 fdiv.h ft3, ft4, ft5, rup
H A Drv64f-valid.s31 # CHECK-ASM-AND-OBJ: fcvt.lu.s a5, ft5, rtz
33 fcvt.lu.s a5, ft5, rtz
H A Drv64zfh-valid.s31 # CHECK-ASM-AND-OBJ: fcvt.lu.h a5, ft5, rtz
33 fcvt.lu.h a5, ft5, rtz
H A Drv64d-valid.s30 # CHECK-ASM-AND-OBJ: fmv.d.x ft5, a5
33 fmv.d.x ft5, a5
H A Drv64d-invalid.s11 fmv.d.x a5, ft5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
H A Drv32zfhmin-valid.s27 # CHECK-ASM-AND-OBJ: flh ft5, 0(s3)

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