| /llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Float/ |
| H A D | d-conv.s | 17 # ASM-AND-OBJ: fcvt.s.d $ft4, $ft11 19 fcvt.s.d $ft4, $ft11 61 # ASM-AND-OBJ: ftintrp.w.d $ft4, $fa3 63 ftintrp.w.d $ft4, $fa3 85 # ASM-AND-OBJ: ftintrne.w.d $fs7, $ft4 87 ftintrne.w.d $fs7, $ft4
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| H A D | f-arith.s | 60 # ASM-AND-OBJ: fabs.s $fs4, $ft4 62 fabs.s $fs4, $ft4 76 # ASM-AND-OBJ: frsqrt.s $fs1, $ft4 78 frsqrt.s $fs1, $ft4
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| H A D | d-arith.s | 85 # ASM-AND-OBJ: fscaleb.d $ft4, $ft6, $fs2 87 fscaleb.d $ft4, $ft6, $fs2
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| /llvm-project-15.0.7/llvm/test/MC/RISCV/ |
| H A D | rv64d-aliases-valid.s | 25 # CHECK-INST: fcvt.d.lu ft4, a4, dyn 26 # CHECK-ALIAS: fcvt.d.lu ft4, a4{{[[:space:]]}} 27 fcvt.d.lu ft4, a4
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| H A D | rv64d-valid.s | 26 # CHECK-ASM-AND-OBJ: fcvt.d.lu ft4, a4, dyn 29 fcvt.d.lu ft4, a4, dyn 40 # CHECK-ASM-AND-OBJ: fcvt.d.lu ft4, a4, rtz 43 fcvt.d.lu ft4, a4, rtz
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| H A D | rv32d-valid.s | 29 # CHECK-ASM-AND-OBJ: fld ft4, 2047(s2) 71 # CHECK-ASM-AND-OBJ: fdiv.d ft3, ft4, ft5, dyn 73 fdiv.d ft3, ft4, ft5, dyn 146 # CHECK-ASM-AND-OBJ: fdiv.d ft3, ft4, ft5, rtz 148 fdiv.d ft3, ft4, ft5, rtz
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| H A D | rv32f-valid.s | 24 # CHECK-ASM-AND-OBJ: flw ft4, 2047(s2) 66 # CHECK-ASM-AND-OBJ: fdiv.s ft3, ft4, ft5, dyn 68 fdiv.s ft3, ft4, ft5, dyn 148 # CHECK-ASM-AND-OBJ: fdiv.s ft3, ft4, ft5, rup 150 fdiv.s ft3, ft4, ft5, rup
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| H A D | rv32zfh-valid.s | 24 # CHECK-ASM-AND-OBJ: flh ft4, 2047(s2) 66 # CHECK-ASM-AND-OBJ: fdiv.h ft3, ft4, ft5, dyn 68 fdiv.h ft3, ft4, ft5, dyn 148 # CHECK-ASM-AND-OBJ: fdiv.h ft3, ft4, ft5, rup 150 fdiv.h ft3, ft4, ft5, rup
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| H A D | rvd-aliases-valid.s | 82 # CHECK-INST: fdiv.d ft3, ft4, ft5, dyn 83 # CHECK-ALIAS: fdiv.d ft3, ft4, ft5{{[[:space:]]}} 84 fdiv.d ft3, ft4, ft5
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| H A D | rv64f-valid.s | 28 # CHECK-ASM-AND-OBJ: fcvt.l.s a4, ft4, rne 30 fcvt.l.s a4, ft4, rne
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| H A D | rv64zfh-valid.s | 28 # CHECK-ASM-AND-OBJ: fcvt.l.h a4, ft4, rne 30 fcvt.l.h a4, ft4, rne
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| H A D | rvzfh-aliases-valid.s | 82 # CHECK-INST: fdiv.h ft3, ft4, ft5, dyn 83 # CHECK-ALIAS: fdiv.h ft3, ft4, ft5{{[[:space:]]}} 84 fdiv.h ft3, ft4, ft5
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| H A D | rv64d-invalid.s | 10 fcvt.d.lu a4, ft4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
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| H A D | rv64zdinx-invalid.s | 15 fcvt.d.lu a4, ft4 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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| H A D | rvf-aliases-valid.s | 145 # CHECK-INST: fdiv.s ft3, ft4, ft5, dyn 146 # CHECK-ALIAS: fdiv.s ft3, ft4, ft5{{[[:space:]]}} 147 fdiv.s ft3, ft4, ft5
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| H A D | rv32zfhmin-valid.s | 24 # CHECK-ASM-AND-OBJ: flh ft4, 2047(s2)
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| H A D | numeric-reg-names-f.s | 30 fsqrt.s fa0, ft4
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| /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/ |
| H A D | calling-conv-vector-float.ll | 36 ; RV64-NEXT: fmv.w.x ft4, a2 41 ; RV64-NEXT: fadd.s ft3, ft4, ft3
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| H A D | fastcc-float.ll | 30 ; CHECK-NEXT: flw ft4, 80(sp)
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| H A D | interrupt-attr.ll | 116 ; CHECK-RV32-F-NEXT: fsw ft4, 108(sp) # 4-byte Folded Spill 165 ; CHECK-RV32-F-NEXT: flw ft4, 108(sp) # 4-byte Folded Reload 219 ; CHECK-RV32-FD-NEXT: fsd ft4, 216(sp) # 8-byte Folded Spill 268 ; CHECK-RV32-FD-NEXT: fld ft4, 216(sp) # 8-byte Folded Reload 361 ; CHECK-RV64-F-NEXT: fsw ft4, 108(sp) # 4-byte Folded Spill 410 ; CHECK-RV64-F-NEXT: flw ft4, 108(sp) # 4-byte Folded Reload 464 ; CHECK-RV64-FD-NEXT: fsd ft4, 216(sp) # 8-byte Folded Spill 618 ; CHECK-RV32-F-NEXT: fsw ft4, 120(sp) # 4-byte Folded Spill 669 ; CHECK-RV32-F-NEXT: flw ft4, 120(sp) # 4-byte Folded Reload 724 ; CHECK-RV32-FD-NEXT: fsd ft4, 224(sp) # 8-byte Folded Spill [all …]
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| H A D | callee-saved-fpr32s.ll | 32 ; ILP32-NEXT: flw ft4, 16(a1) 87 ; ILP32-NEXT: fsw ft4, 16(a1) 102 ; LP64-NEXT: flw ft4, 16(a1) 157 ; LP64-NEXT: fsw ft4, 16(a1) 185 ; ILP32F-NEXT: flw ft4, 16(a1) 240 ; ILP32F-NEXT: fsw ft4, 16(a1) 281 ; LP64F-NEXT: flw ft4, 16(a1) 336 ; LP64F-NEXT: fsw ft4, 16(a1) 377 ; ILP32D-NEXT: flw ft4, 16(a1) 473 ; LP64D-NEXT: flw ft4, 16(a1) [all …]
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| H A D | inline-asm-f-abi-names.ll | 181 ; RV32IF-NEXT: fmv.s ft4, fa0 183 ; RV32IF-NEXT: fcvt.w.s a0, ft4 189 ; RV64IF-NEXT: fmv.s ft4, fa0 191 ; RV64IF-NEXT: fcvt.w.s a0, ft4 201 ; RV32IF-NEXT: fmv.s ft4, fa0 203 ; RV32IF-NEXT: fcvt.w.s a0, ft4 209 ; RV64IF-NEXT: fmv.s ft4, fa0 211 ; RV64IF-NEXT: fcvt.w.s a0, ft4 214 %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft4}"(float %a)
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| H A D | inline-asm-d-abi-names.ll | 181 ; RV32IFD-NEXT: fmv.d ft4, fa0 183 ; RV32IFD-NEXT: fcvt.w.d a0, ft4 189 ; RV64IFD-NEXT: fmv.d ft4, fa0 191 ; RV64IFD-NEXT: fcvt.w.d a0, ft4 201 ; RV32IFD-NEXT: fmv.d ft4, fa0 203 ; RV32IFD-NEXT: fcvt.w.d a0, ft4 209 ; RV64IFD-NEXT: fmv.d ft4, fa0 211 ; RV64IFD-NEXT: fcvt.w.d a0, ft4 214 %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft4}"(double %a)
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| H A D | callee-saved-fpr64s.ll | 28 ; ILP32-NEXT: fld ft4, 32(a1) 83 ; ILP32-NEXT: fsd ft4, 32(a1) 98 ; LP64-NEXT: fld ft4, 32(a1) 153 ; LP64-NEXT: fsd ft4, 32(a1) 181 ; ILP32D-NEXT: fld ft4, 32(a1) 236 ; ILP32D-NEXT: fsd ft4, 32(a1) 277 ; LP64D-NEXT: fld ft4, 32(a1) 332 ; LP64D-NEXT: fsd ft4, 32(a1)
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| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | mangle.cpp | 118 template<int I> void ft4(S5<I>) { } in ft4() function 121 ft4(S5<10>()); in g2() 124 ft4(S5<20>()); in g2()
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