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/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dhalf-fcmp.ll40 ; RV32I-NEXT: fmv.h.x ft1, a0
47 ; RV64I-NEXT: fmv.h.x ft1, a0
64 ; RV32I-NEXT: fmv.h.x ft1, a1
71 ; RV64I-NEXT: fmv.h.x ft1, a1
88 ; RV32I-NEXT: fmv.h.x ft1, a1
95 ; RV64I-NEXT: fmv.h.x ft1, a1
112 ; RV32I-NEXT: fmv.h.x ft1, a0
193 ; RV32I-NEXT: feq.h a0, ft1, ft1
202 ; RV64I-NEXT: feq.h a0, ft1, ft1
392 ; RV32I-NEXT: feq.h a0, ft1, ft1
[all …]
H A Dfloat-bit-preserving-dagcombines.ll21 ; RV32F-NEXT: fmv.w.x ft1, a0
31 ; RV32FD-NEXT: fmv.w.x ft1, a0
41 ; RV64F-NEXT: fmv.w.x ft1, a0
51 ; RV64FD-NEXT: fmv.w.x ft1, a0
95 ; RV32FD-NEXT: fld ft1, 8(sp)
124 ; RV64FD-NEXT: fmv.d.x ft1, a0
143 ; RV32F-NEXT: fmv.w.x ft1, a0
153 ; RV32FD-NEXT: fmv.w.x ft1, a0
163 ; RV64F-NEXT: fmv.w.x ft1, a0
217 ; RV32FD-NEXT: fld ft1, 8(sp)
[all …]
H A Dcalling-conv-vector-float.ll11 ; RV64-NEXT: fmv.w.x ft1, a0
15 ; RV64-NEXT: fadd.s ft0, ft1, ft0
33 ; RV64-NEXT: fmv.w.x ft1, a7
42 ; RV64-NEXT: fadd.s ft1, ft2, ft1
45 ; RV64-NEXT: fsw ft1, 8(a0)
53 ; RV64LP64F-NEXT: fadd.s ft1, fa1, fa5
58 ; RV64LP64F-NEXT: fsw ft1, 4(a0)
H A Dselect-optimize-multiple.ll276 ; RV32I-NEXT: fmv.w.x ft1, a2
280 ; RV32I-NEXT: fmv.w.x ft1, a1
292 ; RV32IBT-NEXT: fmv.w.x ft1, a2
296 ; RV32IBT-NEXT: fmv.w.x ft1, a1
308 ; RV64I-NEXT: fmv.w.x ft1, a2
312 ; RV64I-NEXT: fmv.w.x ft1, a1
542 ; RV32I-NEXT: fmv.w.x ft1, a0
550 ; RV32I-NEXT: fmv.s ft0, ft1
567 ; RV32IBT-NEXT: fmv.s ft0, ft1
576 ; RV64I-NEXT: fmv.w.x ft1, a0
[all …]
H A Dcalling-conv-rv32f-ilp32.ll22 ; RV32IF-NEXT: flw ft1, 0(sp)
23 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0
60 ; RV32IF-NEXT: fmv.w.x ft1, a0
61 ; RV32IF-NEXT: fadd.s ft2, ft1, ft0
62 ; RV32IF-NEXT: fsub.s ft0, ft0, ft1
H A Ddouble-stack-spill-restore.ll26 ; RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
27 ; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
49 ; RV64IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload
50 ; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
H A Ddouble-calling-conv.ll19 ; RV32IFD-NEXT: fld ft1, 8(sp)
20 ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
62 ; RV32IFD-NEXT: fld ft1, 8(sp)
63 ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
104 ; RV32IFD-NEXT: fld ft1, 16(sp)
105 ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
/llvm-project-15.0.7/clang/test/CXX/temp/temp.spec/temp.expl.spec/
H A Dp2.cpp70 void ft1(T t, U u);
77 void N0::X0<T>::ft1(T t, U u) { in ft1() function in N0::X0
215 void X0<void*>::ft1(void*, const void*) { } in ft1() function in N0::X0
218 void X0<void*>::ft1(void *, int);
221 void X0<void*>::ft1(void *, unsigned);
224 void X0<void*>::ft1(void *, long);
228 void N0::X0<void*>::ft1(void *, unsigned) { } // okay in ft1() function in N0::X0
231 void N0::X0<void*>::ft1(void *, float) { } in ft1() function in N0::X0
241 xvp.ft1(vp, cvp); in test_func_template()
242 xvp.ft1(vp, i); in test_func_template()
[all …]
H A Dp2-0x.cpp64 void ft1(T t, U u);
71 void N0::X0<T>::ft1(T t, U u) { in ft1() function in N0::X0
247 void X0<void*>::ft1(void*, const void*) { } in ft1() function in N0::X0
250 void X0<void*>::ft1(void *, int);
253 void X0<void*>::ft1(void *, unsigned);
256 void X0<void*>::ft1(void *, long);
260 void N0::X0<void*>::ft1(void *, unsigned) { } // okay in ft1() function in N0::X0
263 void N0::X0<void*>::ft1(void *, float) { } in ft1() function in N0::X0
273 xvp.ft1(vp, cvp); in test_func_template()
274 xvp.ft1(vp, i); in test_func_template()
[all …]
H A Dp1.cpp43 void ft1(T t, U u);
48 void X0<T>::ft1(T t, U u) { in ft1() function in X0
89 void X0<void*>::ft1(void*, const void*) { } in ft1() function in X0
92 xvp.ft1(vp, cvp); in test_func_template()
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drvzfh-aliases-valid.s26 # CHECK-INST: fsgnj.h ft0, ft1, ft1
27 # CHECK-ALIAS: fmv.h ft0, ft1
29 # CHECK-INST: fsgnjx.h ft1, ft2, ft2
30 # CHECK-ALIAS: fabs.h ft1, ft2
46 # CHECK-INST: fmv.h.x ft1, a6
47 # CHECK-ALIAS: fmv.h.x ft1, a6
48 fmv.h.x ft1, a6
79 # CHECK-INST: fmul.h ft0, ft1, ft2, dyn
80 # CHECK-ALIAS: fmul.h ft0, ft1, ft2{{[[:space:]]}}
81 fmul.h ft0, ft1, ft2
H A Drvd-aliases-valid.s33 # CHECK-INST: fsgnj.d ft0, ft1, ft1
34 # CHECK-ALIAS: fmv.d ft0, ft1
36 # CHECK-INST: fsgnjx.d ft1, ft2, ft2
37 # CHECK-ALIAS: fabs.d ft1, ft2
79 # CHECK-INST: fmul.d ft0, ft1, ft2, dyn
80 # CHECK-ALIAS: fmul.d ft0, ft1, ft2{{[[:space:]]}}
81 fmul.d ft0, ft1, ft2
H A Drv64zfh-invalid.s6 flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tpre…
10 flw ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
12 fld ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
17 fcvt.lu.h ft1, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
H A Drvf-aliases-valid.s33 # CHECK-INST: fsgnj.s ft0, ft1, ft1
34 # CHECK-ALIAS: fmv.s ft0, ft1
36 # CHECK-INST: fsgnjx.s ft1, ft2, ft2
37 # CHECK-ALIAS: fabs.s ft1, ft2
109 # CHECK-INST: fmv.w.x ft1, a6
110 # CHECK-ALIAS: fmv.w.x ft1, a6
111 fmv.s.x ft1, a6
142 # CHECK-INST: fmul.s ft0, ft1, ft2, dyn
143 # CHECK-ALIAS: fmul.s ft0, ft1, ft2{{[[:space:]]}}
144 fmul.s ft0, ft1, ft2
H A Drv32f-invalid.s5 flw ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tpre…
9 flw ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
14 flw ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
32 fadd.d ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-…
H A Drv32d-invalid.s5 fld ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tpre…
9 fld ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
14 fld ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
H A Drv32zfhmin-invalid.s8 flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tpre…
12 flh ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
16 flh ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
H A Drv64d-aliases-valid.s19 # CHECK-INST: fcvt.lu.d a1, ft1, dyn
20 # CHECK-ALIAS: fcvt.lu.d a1, ft1{{[[:space:]]}}
21 fcvt.lu.d a1, ft1
H A Drv64f-aliases-valid.s19 # CHECK-INST: fcvt.lu.s a1, ft1, dyn
20 # CHECK-ALIAS: fcvt.lu.s a1, ft1{{[[:space:]]}}
21 fcvt.lu.s a1, ft1
H A Drv64d-valid.s14 # CHECK-ASM-AND-OBJ: fcvt.lu.d a1, ft1, dyn
17 fcvt.lu.d a1, ft1, dyn
48 # CHECK-ASM-AND-OBJ: fcvt.lu.d a1, ft1, rup
51 fcvt.lu.d a1, ft1, rup
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dfround-sdnode.ll13 ; CHECK-NEXT: flh ft1, %lo(.LCPI0_1)(a0)
17 ; CHECK-NEXT: vfadd.vf v9, v9, ft1
38 ; CHECK-NEXT: vfadd.vf v9, v9, ft1
59 ; CHECK-NEXT: vfadd.vf v9, v9, ft1
80 ; CHECK-NEXT: vfadd.vf v10, v10, ft1
101 ; CHECK-NEXT: vfadd.vf v12, v12, ft1
122 ; CHECK-NEXT: vfadd.vf v16, v16, ft1
143 ; CHECK-NEXT: vfadd.vf v9, v9, ft1
164 ; CHECK-NEXT: vfadd.vf v9, v9, ft1
185 ; CHECK-NEXT: vfadd.vf v10, v10, ft1
[all …]
H A Dffloor-sdnode.ll17 ; CHECK-NEXT: flh ft1, %lo(.LCPI0_1)(a0)
21 ; CHECK-NEXT: vmflt.vf v0, v10, ft1
44 ; CHECK-NEXT: vmflt.vf v0, v10, ft1
67 ; CHECK-NEXT: vmflt.vf v0, v10, ft1
90 ; CHECK-NEXT: vmflt.vf v0, v12, ft1
113 ; CHECK-NEXT: vmflt.vf v0, v16, ft1
136 ; CHECK-NEXT: vmflt.vf v0, v24, ft1
159 ; CHECK-NEXT: vmflt.vf v0, v10, ft1
182 ; CHECK-NEXT: vmflt.vf v0, v10, ft1
205 ; CHECK-NEXT: vmflt.vf v0, v12, ft1
[all …]
H A Dfceil-sdnode.ll17 ; CHECK-NEXT: flh ft1, %lo(.LCPI0_1)(a0)
21 ; CHECK-NEXT: vmflt.vf v0, v10, ft1
44 ; CHECK-NEXT: vmflt.vf v0, v10, ft1
67 ; CHECK-NEXT: vmflt.vf v0, v10, ft1
90 ; CHECK-NEXT: vmflt.vf v0, v12, ft1
113 ; CHECK-NEXT: vmflt.vf v0, v16, ft1
136 ; CHECK-NEXT: vmflt.vf v0, v24, ft1
159 ; CHECK-NEXT: vmflt.vf v0, v10, ft1
182 ; CHECK-NEXT: vmflt.vf v0, v10, ft1
205 ; CHECK-NEXT: vmflt.vf v0, v12, ft1
[all …]
H A Dfptoui-sat.ll79 ; CHECK-NEXT: fmv.w.x ft1, zero
81 ; CHECK-NEXT: vfmax.vf v8, v8, ft1
95 ; CHECK-NEXT: fmv.w.x ft1, zero
97 ; CHECK-NEXT: vfmax.vf v8, v8, ft1
161 ; CHECK32-NEXT: fcvt.d.w ft1, zero
173 ; CHECK64-NEXT: fmv.d.x ft1, zero
189 ; CHECK32-NEXT: fcvt.d.w ft1, zero
201 ; CHECK64-NEXT: fmv.d.x ft1, zero
229 ; CHECK64-NEXT: fmv.d.x ft1, zero
259 ; CHECK64-NEXT: fmv.d.x ft1, zero
[all …]
/llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Float/
H A Df-arith.s52 # ASM-AND-OBJ: fmaxa.s $ft1, $fs3, $fs7
54 fmaxa.s $ft1, $fs3, $fs7
92 # ASM-AND-OBJ: fclass.s $ft12, $ft1
94 fclass.s $ft12, $ft1

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