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/llvm-project-15.0.7/clang/test/Sema/
H A Dattr-arm-sve-vector-bits.c124 fixed_int8_t fs8; in f() local
144 …fs8 = fs8 + ss8; // expected-error {{cannot combine fixed-length and sizeless SVE vectors in expre… in f()
145 …fs8 = fs8 + gs8; // expected-error {{cannot combine GNU and SVE vectors in expression, result is a… in f()
148 …gs8 = gs8 + fs8; // expected-error {{cannot combine GNU and SVE vectors in expression, result is a… in f()
154 …fs8 += gs8; // expected-error {{cannot combine GNU and SVE vectors in expression, result is ambigu… in f()
157 …gs8 += fs8; // expected-error {{cannot combine GNU and SVE vectors in expression, result is ambigu… in f()
162 …fs8 = fs8 == ss8; // expected-error {{cannot combine fixed-length and sizeless SVE vectors in expr… in f()
163 …fs8 = fs8 == gs8; // expected-error {{cannot combine GNU and SVE vectors in expression, result is … in f()
171 …fs8 = fs8 & ss8; // expected-error {{cannot combine fixed-length and sizeless SVE vectors in expre… in f()
172 …fs8 = fs8 & gs8; // expected-error {{cannot combine GNU and SVE vectors in expression, result is a… in f()
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drv32d-valid.s58 # CHECK-ASM-AND-OBJ: fnmadd.d fs6, fs7, fs8, fs9, dyn
96 # CHECK-ASM-AND-OBJ: fcvt.d.s fs7, fs8
98 fcvt.d.s fs7, fs8
99 # CHECK-ASM-AND-OBJ: feq.d a1, fs8, fs9
101 feq.d a1, fs8, fs9
133 # CHECK-ASM-AND-OBJ: fnmadd.d fs6, fs7, fs8, fs9, rup
H A Drv32f-valid.s53 # CHECK-ASM-AND-OBJ: fnmadd.s fs6, fs7, fs8, fs9, dyn
96 # CHECK-ASM-AND-OBJ: feq.s a1, fs8, fs9
98 feq.s a1, fs8, fs9
129 # CHECK-ASM-AND-OBJ: fnmadd.s fs6, fs7, fs8, fs9, rup
H A Drv32zfh-valid.s53 # CHECK-ASM-AND-OBJ: fnmadd.h fs6, fs7, fs8, fs9, dyn
96 # CHECK-ASM-AND-OBJ: feq.h a1, fs8, fs9
98 feq.h a1, fs8, fs9
129 # CHECK-ASM-AND-OBJ: fnmadd.h fs6, fs7, fs8, fs9, rup
H A Drvd-aliases-valid.s70 # CHECK-INST: fnmadd.d fs6, fs7, fs8, fs9, dyn
71 # CHECK-ALIAS: fnmadd.d fs6, fs7, fs8, fs9{{[[:space:]]}}
H A Drvzfh-aliases-valid.s70 # CHECK-INST: fnmadd.h fs6, fs7, fs8, fs9, dyn
71 # CHECK-ALIAS: fnmadd.h fs6, fs7, fs8, fs9{{[[:space:]]}}
H A Drvf-aliases-valid.s133 # CHECK-INST: fnmadd.s fs6, fs7, fs8, fs9, dyn
134 # CHECK-ALIAS: fnmadd.s fs6, fs7, fs8, fs9{{[[:space:]]}}
H A Dnumeric-reg-names-f.s130 fsqrt.s fa0, fs8
H A Dnumeric-reg-names-d.s130 fsqrt.d fa0, fs8
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dcallee-saved-fpr32s.ll56 ; ILP32-NEXT: flw fs8, 124(a1)
60 ; ILP32-NEXT: fsw fs8, 124(a1)
126 ; LP64-NEXT: flw fs8, 124(a1)
130 ; LP64-NEXT: fsw fs8, 124(a1)
209 ; ILP32F-NEXT: flw fs8, 124(a1)
213 ; ILP32F-NEXT: fsw fs8, 124(a1)
305 ; LP64F-NEXT: flw fs8, 124(a1)
309 ; LP64F-NEXT: fsw fs8, 124(a1)
497 ; LP64D-NEXT: flw fs8, 124(a1)
501 ; LP64D-NEXT: fsw fs8, 124(a1)
[all …]
H A Dfastcc-float.ll46 ; CHECK-NEXT: flw fs8, 144(sp)
56 ; CHECK-NEXT: fsw fs8, 32(sp)
H A Dcallee-saved-fpr64s.ll52 ; ILP32-NEXT: fld fs8, 248(a1)
56 ; ILP32-NEXT: fsd fs8, 248(a1)
122 ; LP64-NEXT: fld fs8, 248(a1)
126 ; LP64-NEXT: fsd fs8, 248(a1)
205 ; ILP32D-NEXT: fld fs8, 248(a1)
209 ; ILP32D-NEXT: fsd fs8, 248(a1)
301 ; LP64D-NEXT: fld fs8, 248(a1)
305 ; LP64D-NEXT: fsd fs8, 248(a1)
710 ; ILP32D-NEXT: fld fs8, 160(s1)
853 ; LP64D-NEXT: fld fs8, 160(s1)
[all …]
H A Dinline-asm-f-abi-names.ll1124 ; RV32IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
1125 ; RV32IF-NEXT: fmv.s fs8, fa0
1127 ; RV32IF-NEXT: fcvt.w.s a0, fs8
1136 ; RV64IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
1137 ; RV64IF-NEXT: fmv.s fs8, fa0
1139 ; RV64IF-NEXT: fcvt.w.s a0, fs8
1153 ; RV32IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
1154 ; RV32IF-NEXT: fmv.s fs8, fa0
1156 ; RV32IF-NEXT: fcvt.w.s a0, fs8
1166 ; RV64IF-NEXT: fmv.s fs8, fa0
[all …]
H A Dinline-asm-d-abi-names.ll1124 ; RV32IFD-NEXT: fsd fs8, 8(sp) # 8-byte Folded Spill
1125 ; RV32IFD-NEXT: fmv.d fs8, fa0
1127 ; RV32IFD-NEXT: fcvt.w.d a0, fs8
1136 ; RV64IFD-NEXT: fsd fs8, 8(sp) # 8-byte Folded Spill
1137 ; RV64IFD-NEXT: fmv.d fs8, fa0
1139 ; RV64IFD-NEXT: fcvt.w.d a0, fs8
1153 ; RV32IFD-NEXT: fsd fs8, 8(sp) # 8-byte Folded Spill
1154 ; RV32IFD-NEXT: fmv.d fs8, fa0
1156 ; RV32IFD-NEXT: fcvt.w.d a0, fs8
1166 ; RV64IFD-NEXT: fmv.d fs8, fa0
[all …]
H A Dghccc-rv32.ll27 @d3 = external global double ; assigned to register: fs8
42 ; CHECK-NEXT: fld fs8, %lo(d3)(a0)
H A Dghccc-rv64.ll27 @d3 = external global double ; assigned to register: fs8
42 ; CHECK-NEXT: fld fs8, %lo(d3)(a0)
H A Dinterrupt-attr.ll140 ; CHECK-RV32-F-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
189 ; CHECK-RV32-F-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload
243 ; CHECK-RV32-FD-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill
292 ; CHECK-RV32-FD-NEXT: fld fs8, 24(sp) # 8-byte Folded Reload
385 ; CHECK-RV64-F-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
434 ; CHECK-RV64-F-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload
488 ; CHECK-RV64-FD-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill
642 ; CHECK-RV32-F-NEXT: fsw fs8, 24(sp) # 4-byte Folded Spill
693 ; CHECK-RV32-F-NEXT: flw fs8, 24(sp) # 4-byte Folded Reload
748 ; CHECK-RV32-FD-NEXT: fsd fs8, 32(sp) # 8-byte Folded Spill
[all …]
H A Dinterrupt-attr-nocall.ll460 ; CHECK-RV32IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill
518 ; CHECK-RV32IF-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload
653 ; CHECK-RV32IF-NEXT: fsw fs8, 24(sp) # 4-byte Folded Spill
713 ; CHECK-RV32IF-NEXT: flw fs8, 24(sp) # 4-byte Folded Reload
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Daarch64-sve-fixedtypeinfo.cpp41 auto &fs8 = typeid(fixed_int8_t); variable
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td206 def F24_H : RISCVReg16<24,"f24", ["fs8"]>, DwarfRegNum<[56]>;