Home
last modified time | relevance | path

Searched refs:force (Results 1 – 25 of 929) sorted by relevance

12345678910>>...38

/llvm-project-15.0.7/flang/include/flang/Lower/
H A DSymbolMap.h204 bool force = false);
219 makeSym(sym, value, force);
230 makeSym(sym, value, force);
243 makeSym(sym, value, force);
256 makeSym(sym, value, force);
270 makeSym(sym, value, force);
275 makeSym(sym, box, force);
285 force);
289 makeSym(sym, value, force);
344 bool force = false) {
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/ForcedFunctionAttrs/
H A Dforced.ll2 ; RUN: opt < %s -S -forceattrs -force-attribute foo:noinline | FileCheck %s --check-prefix=CHECK-FOO
3 ; RUN: opt < %s -S -passes=forceattrs -force-attribute foo:noinline | FileCheck %s --check-prefix=C…
4 ; RUN: opt < %s -S -passes=forceattrs -force-remove-attribute goo:cold | FileCheck %s --check-prefi…
5 ; RUN: opt < %s -S -passes=forceattrs -force-remove-attribute goo:noinline | FileCheck %s --check-p…
6 ; RUN: opt < %s -S -passes=forceattrs -force-attribute goo:cold -force-remove-attribute goo:noinlin…
7 ; RUN: opt < %s -S -passes=forceattrs -force-attribute goo:noinline -force-remove-attribute goo:noi…
24 ; `force-remove` takes precedence over `force`.
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dvector-freeze.ll1 ; RUN: opt -loop-vectorize -force-vector-width=16 -force-vector-interleave=1 -S < %s | FileCheck %s
2 …p-vectorize -scalable-vectorization=on -force-target-supports-scalable-vectors=true -force-vector-…
H A Dopt.ll1 ; RUN: opt -S -O3 -force-vector-width=2 -force-vector-interleave=1 < %s | FileCheck --check-prefix=…
2 ; RUN: opt -S -O3 -vectorize-loops=false -force-vector-width=2 -force-vector-interleave=1 < %s | Fi…
H A Ddiscriminator.ll1 ; RUN: opt -S -loop-vectorize -force-vector-width=4 -force-vector-interleave=1 < %s | FileCheck --c…
2 ; RUN: opt -S -loop-vectorize -force-vector-width=2 -force-vector-interleave=3 < %s | FileCheck --c…
4 ; RUN: opt -S -loop-vectorize -force-vector-width=4 -force-vector-interleave=4 -loop-unroll -unroll…
H A Dcast-induction.ll1 ; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -S %s | FileChec…
2 ; RUN: opt -passes=loop-vectorize -force-vector-interleave=2 -force-vector-width=1 -S %s | FileChec…
H A Dunroll_novec.ll1 …opt < %s -loop-vectorize -force-vector-width=1 -force-target-num-scalar-regs=16 -force-target-max…
/llvm-project-15.0.7/lld/test/MachO/
H A Dforce-load.s10 # RUN: %lld -lSystem -force_load %t/foo.a %t/foo.o %t/test.o -o %t/test-force-load-first
12 # RUN: llvm-objdump --syms %t/test-force-load-first | FileCheck %s --check-prefix=FORCE-LOAD-FIRST
14 # RUN: %lld %t/foo.o -lSystem -force_load %t/foo.a %t/test.o -o %t/test-force-load-second
15 # RUN: llvm-objdump --syms %t/test-force-load-second | FileCheck %s --check-prefix=FORCE-LOAD-SECOND
20 # RUN: %lld -lSystem %t/foo.a -force_load %t/foo.a %t/test.o -o %t/test-regular-then-force
21 # RUN: llvm-objdump --syms %t/test-regular-then-force | FileCheck %s --check-prefix=REGULAR-THEN-FO…
24 # RUN: %lld -lSystem -force_load %t/foo.a %t/foo.a %t/test.o -o %t/test-force-then-regular
25 # RUN: llvm-objdump --syms %t/test-force-then-regular | FileCheck %s --check-prefix=FORCE-THEN-REGU…
/llvm-project-15.0.7/flang/lib/Lower/
H A DSymbolMap.cpp21 bool force) { in addSymbol() argument
22 exv.match([&](const fir::UnboxedValue &v) { addSymbol(sym, v, force); }, in addSymbol()
23 [&](const fir::CharBoxValue &v) { makeSym(sym, v, force); }, in addSymbol()
24 [&](const fir::ArrayBoxValue &v) { makeSym(sym, v, force); }, in addSymbol()
25 [&](const fir::CharArrayBoxValue &v) { makeSym(sym, v, force); }, in addSymbol()
26 [&](const fir::BoxValue &v) { makeSym(sym, v, force); }, in addSymbol()
27 [&](const fir::MutableBoxValue &v) { makeSym(sym, v, force); }, in addSymbol()
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dsve-strict-fadd-cost.ll2 ; RUN: opt < %s -loop-vectorize -debug -disable-output -force-ordered-reductions=true -hints-allow-…
3 ; RUN: -prefer-predicate-over-epilogue=scalar-epilogue -force-vector-width=4 -force-vector-interl…
5 ; RUN: opt < %s -loop-vectorize -debug -disable-output -force-ordered-reductions=true -hints-allow-…
6 ; RUN: -prefer-predicate-over-epilogue=scalar-epilogue -force-vector-width=8 -force-vector-interl…
8 ; RUN: opt < %s -loop-vectorize -debug -disable-output -force-ordered-reductions=true -hints-allow-…
9 ; RUN: -prefer-predicate-over-epilogue=scalar-epilogue -force-vector-width=4 -force-vector-interl…
H A Dscalarize-store-with-predication.ll1 ; RUN: opt -loop-vectorize -force-vector-width=1 -force-vector-interleave=2 \
3 ; RUN: opt -mattr=+sve -loop-vectorize -force-vector-width=1 -force-vector-interleave=2 \
12 ; This test checks that, when we disable vectorisation and force interleaving,
H A Dscalable-vectorization-cost-tuning.ll3 ; RUN: -force-target-instruction-cost=1 -loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1…
7 ; RUN: -force-target-instruction-cost=1 -loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1…
11 ; RUN: -force-target-instruction-cost=1 -loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1…
15 ; RUN: -force-target-instruction-cost=1 -loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1…
19 ; RUN: -force-target-instruction-cost=1 -loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1…
/llvm-project-15.0.7/lld/test/COFF/
H A Dmerge.test2 # RUN: lld-link /out:%t.exe /entry:main /subsystem:console /force \
6 # RUN: lld-link /out:%t.exe /entry:main /subsystem:console /force \
10 # RUN: env LLD_IN_TEST=1 not lld-link /out:%t.exe /entry:main /subsystem:console /force \
12 # RUN: env LLD_IN_TEST=1 not lld-link /out:%t.exe /entry:main /subsystem:console /force \
14 # RUN: env LLD_IN_TEST=1 not lld-link /out:%t.exe /entry:main /subsystem:console /force \
16 # RUN: env LLD_IN_TEST=1 not lld-link /out:%t.exe /entry:main /subsystem:console /force \
18 # RUN: env LLD_IN_TEST=1 not lld-link /out:%t.exe /entry:main /subsystem:console /force \
20 # RUN: env LLD_IN_TEST=1 not lld-link /out:%t.exe /entry:main /subsystem:console /force \
H A Dfunctionpadmin.test2 RUN: lld-link %S/Inputs/precomp-a.obj /out:%t.exe /nodefaultlib /force
5 RUN: lld-link %S/Inputs/precomp-a.obj /out:%t.exe /nodefaultlib /force /functionpadmin
8 RUN: lld-link %S/Inputs/precomp-a.obj /out:%t.exe /nodefaultlib /force /functionpadmin:17
12 RUN: lld-link %S/Inputs/precomp-a.obj /out:%t.exe /nodefaultlib /force /functionpadmin:17 /function…
15 RUN: lld-link %S/Inputs/precomp-a.obj /out:%t.exe /nodefaultlib /force /functionpadmin /functionpad…
18 RUN: not lld-link %S/Inputs/precomp-a.obj /out:%t.exe /nodefaultlib /force /functionpadmin:zz 2>&1 …
21 …Inputs/precomp-a.obj %S/Inputs/precomp-b.obj %S/Inputs/precomp.obj /out:%t.exe /nodefaultlib /force
31 RUN: lld-link %S/Inputs/pdb-diff.obj /out:%t.exe /nodefaultlib /force /functionpadmin
35 RUN: lld-link %S/Inputs/hello64.obj /out:%t.exe /nodefaultlib /force /functionpadmin
39 RUN: lld-link %S/Inputs/std64.lib /entry:ExitProcess /out:%t.exe /nodefaultlib /force /subsystem:co…
[all …]
H A Dforce-multipleres.test2 // /force or /force:multipleres is passed.
23 RUN: lld-link /force /machine:x64 /nodefaultlib /noentry /dll %t.dir/id1.res %t.dir/id2.res 2>&1 | \
25 RUN: lld-link /force:multipleres /machine:x64 /nodefaultlib /noentry /dll %t.dir/id1.res %t.dir/id2…
27 RUN: lld-link /lldmingw /force:multipleres /machine:x64 /nodefaultlib /noentry /dll %t.dir/id1.o %t…
H A Dsection.test2 # RUN: lld-link /out:%t.exe /entry:main /subsystem:console /force \
6 # RUN: lld-link /out:%t.exe /entry:main /subsystem:console /force \
10 # RUN: lld-link /out:%t.exe /entry:main /subsystem:console /force \
14 # RUN: lld-link /out:%t.exe /entry:main /subsystem:console /force \
/llvm-project-15.0.7/lldb/source/Plugins/Platform/MacOSX/
H A DPlatformAppleSimulator.cpp294 CoreSimulatorSupport::DeviceType::ProductFamilyID kind, bool force, in CreateInstance() argument
308 force ? "true" : "false", arch_name, triple_cstr); in CreateInstance()
311 bool create = force; in CreateInstance()
525 return !force && arch && arch->IsValid() && in shouldSkipSimulatorPlatform()
543 static PlatformSP CreateInstance(bool force, const ArchSpec *arch) { in CreateInstance()
544 if (shouldSkipSimulatorPlatform(force, arch)) in CreateInstance()
588 static PlatformSP CreateInstance(bool force, const ArchSpec *arch) { in CreateInstance()
589 if (shouldSkipSimulatorPlatform(force, arch)) in CreateInstance()
608 CoreSimulatorSupport::DeviceType::ProductFamilyID::appleTV, force, in CreateInstance()
630 static PlatformSP CreateInstance(bool force, const ArchSpec *arch) { in CreateInstance()
[all …]
H A DPlatformRemoteAppleWatch.cpp57 PlatformSP PlatformRemoteAppleWatch::CreateInstance(bool force, in CreateInstance() argument
71 __FUNCTION__, force ? "true" : "false", arch_name, triple_cstr); in CreateInstance()
74 bool create = force; in CreateInstance()
121 if (force == false) { in CreateInstance()
/llvm-project-15.0.7/llvm/test/Transforms/HardwareLoops/
H A Dunconditional-latch.ll1 ; RUN: opt -force-hardware-loops=true -hardware-loop-decrement=1 -hardware-loop-counter-bitwidth=32…
2 ; RUN: opt -force-hardware-loops=true -hardware-loop-decrement=1 -hardware-loop-counter-bitwidth=32…
3 ; RUN: opt -force-hardware-loops=true -hardware-loop-decrement=1 -hardware-loop-counter-bitwidth=32…
H A Dunscevable.ll1 ; RUN: opt -hardware-loops -force-hardware-loops=true -hardware-loop-decrement=1 -hardware-loop-cou…
2 ; RUN: opt -hardware-loops -force-hardware-loops=true -hardware-loop-decrement=1 -hardware-loop-cou…
3 ; RUN: opt -hardware-loops -force-hardware-loops=true -hardware-loop-decrement=1 -hardware-loop-cou…
/llvm-project-15.0.7/polly/test/CodeGen/OpenMP/
H A Dsingle_loop_with_loop_invariant_baseptr.ll1 ; RUN: opt %loadPolly -tbaa -polly-parallel -polly-parallel-force -polly-parallel-force -polly-inva…
2 ; RUN: opt %loadPolly -tbaa -polly-parallel -polly-parallel-force -polly-parallel-force -polly-inva…
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterContextDarwin_arm64.h185 int ReadGPR(bool force);
187 int ReadFPU(bool force);
189 int ReadEXC(bool force);
191 int ReadDBG(bool force);
218 int ReadRegisterSet(uint32_t set, bool force);
H A DRegisterContextDarwin_arm.h218 int ReadGPR(bool force);
220 int ReadFPU(bool force);
222 int ReadEXC(bool force);
224 int ReadDBG(bool force);
251 int ReadRegisterSet(uint32_t set, bool force);
/llvm-project-15.0.7/llvm/test/Instrumentation/AddressSanitizer/
H A Dforce-dynamic-shadow.ll1 ; Test -asan-force-dynamic-shadow flag.
3 ; RUN: opt -passes='asan-pipeline' -S -asan-force-dynamic-shadow=1 < %s | FileCheck %s --check-pref…
4 ; RUN: opt -passes='asan-pipeline' -S -asan-force-dynamic-shadow=0 < %s | FileCheck %s --check-pref…
/llvm-project-15.0.7/lld/test/ELF/
H A Daarch64-bti-pac-cli-error.s3 # RUN: not ld.lld -z pac-plt -z force-bti -z bti-report=error %t.o -o /dev/null 2>&1 | FileCheck %s
5 ## Check that we error if -z pac-plt, -z force-bti and -z bti-report=error are used when target is …
9 # CHECK-NEXT: error: -z force-bti only supported on AArch64

12345678910>>...38