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/llvm-project-15.0.7/llvm/test/Analysis/CostModel/X86/
H A Dreduce-fmin.ll154 declare double @llvm.vector.reduce.fmin.v1f64(<1 x double>)
155 declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
156 declare double @llvm.vector.reduce.fmin.v4f64(<4 x double>)
157 declare double @llvm.vector.reduce.fmin.v8f64(<8 x double>)
158 declare double @llvm.vector.reduce.fmin.v16f64(<16 x double>)
160 declare float @llvm.vector.reduce.fmin.v1f32(<1 x float>)
161 declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>)
162 declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
163 declare float @llvm.vector.reduce.fmin.v8f32(<8 x float>)
164 declare float @llvm.vector.reduce.fmin.v16f32(<16 x float>)
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/SVE/
H A Dfmin.s18 fmin z0.h, p0/m, z0.h, #0.0 label
24 fmin z0.s, p0/m, z0.s, #0.0 label
30 fmin z0.d, p0/m, z0.d, #0.0 label
42 fmin z31.h, p7/m, z31.h, #1.0 label
48 fmin z31.s, p7/m, z31.s, #1.0 label
54 fmin z31.d, p7/m, z31.d, #1.0 label
60 fmin z0.h, p7/m, z0.h, z31.h label
66 fmin z0.s, p7/m, z0.s, z31.s label
72 fmin z0.d, p7/m, z0.d, z31.d label
112 fmin z0.d, p7/m, z0.d, z31.d label
[all …]
H A Dfmin-diagnostics.s6 fmin z0.h, p0/m, z0.h, #0.5 label
11 fmin z0.h, p0/m, z0.h, #-0.0 label
16 fmin z0.h, p0/m, z0.h, #0.0000000000000000000000001 label
21 fmin z0.h, p0/m, z0.h, #1.0000000000000000000000001 label
26 fmin z0.h, p0/m, z0.h, #0.9999999999999999999999999 label
35 fmin z0.h, p7/m, z1.h, z31.h label
44 fmin z0.b, p7/m, z0.b, z31.b label
49 fmin z0.h, p7/m, z0.h, z31.s label
58 fmin z0.h, p8/m, z0.h, z31.h label
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dmath-intrins-sm80-ptx70-instcombine.ll5 declare half @llvm.nvvm.fmin.f16(half, half)
35 ; CHECK-NOT: @llvm.nvvm.fmin.f16
43 ; CHECK-NOT: @llvm.nvvm.fmin.ftz.f16
52 ; CHECK: @llvm.nvvm.fmin.ftz.f16
59 ; CHECK-NOT: @llvm.nvvm.fmin.f16x2
67 ; CHECK-NOT: @llvm.nvvm.fmin.ftz.f16x2
76 ; CHECK: @llvm.nvvm.fmin.ftz.f16x2
83 ; CHECK-NOT: @llvm.nvvm.fmin.nan.f
99 ; CHECK: @llvm.nvvm.fmin.ftz.nan.f
107 ; CHECK-NOT: @llvm.nvvm.fmin.nan.f16
[all …]
H A Dmath-intrins-sm86-ptx72.ll4 declare half @llvm.nvvm.fmin.xorsign.abs.f16(half, half)
5 declare half @llvm.nvvm.fmin.ftz.xorsign.abs.f16(half, half)
6 declare half @llvm.nvvm.fmin.nan.xorsign.abs.f16(half, half)
7 declare half @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16(half, half)
12 declare i16 @llvm.nvvm.fmin.xorsign.abs.bf16(i16, i16)
13 declare i16 @llvm.nvvm.fmin.nan.xorsign.abs.bf16(i16, i16)
14 declare i32 @llvm.nvvm.fmin.xorsign.abs.bf16x2(i32, i32)
15 declare i32 @llvm.nvvm.fmin.nan.xorsign.abs.bf16x2(i32, i32)
16 declare float @llvm.nvvm.fmin.xorsign.abs.f(float, float)
17 declare float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float, float)
[all …]
H A Dmath-intrins-sm80-ptx70.ll9 declare float @llvm.nvvm.fmin.nan.f(float, float)
10 declare float @llvm.nvvm.fmin.ftz.nan.f(float, float)
11 declare half @llvm.nvvm.fmin.f16(half, half)
12 declare half @llvm.nvvm.fmin.ftz.f16(half, half)
13 declare half @llvm.nvvm.fmin.nan.f16(half, half)
14 declare half @llvm.nvvm.fmin.ftz.nan.f16(half, half)
19 declare i16 @llvm.nvvm.fmin.bf16(i16, i16)
20 declare i16 @llvm.nvvm.fmin.nan.bf16(i16, i16)
21 declare i32 @llvm.nvvm.fmin.bf16x2(i32, i32)
22 declare i32 @llvm.nvvm.fmin.nan.bf16x2(i32, i32)
[all …]
/llvm-project-15.0.7/libclc/amdgcn/lib/math/
H A Dfmin.cl5 _CLC_DEF _CLC_OVERLOAD float fmin(float x, float y)
8 * Otherwise fmin instruction flushes the values for comparison,
14 _CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, fmin, float, float)
20 _CLC_DEF _CLC_OVERLOAD double fmin(double x, double y)
26 _CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, fmin, double, double)
33 _CLC_DEF _CLC_OVERLOAD half fmin(half x, half y)
41 _CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, fmin, half, half)
45 #define __CLC_BODY <../../../generic/lib/math/fmin.inc>
/llvm-project-15.0.7/libclc/generic/lib/math/
H A Dfmin.inc4 _CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE fmin(__CLC_GENTYPE x, float y) {
5 return fmin(x, (__CLC_GENTYPE)((__CLC_SCALAR_GENTYPE)y));
12 _CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE fmin(__CLC_GENTYPE x, double y) {
13 return fmin(x, (__CLC_GENTYPE)((__CLC_SCALAR_GENTYPE)y));
22 _CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE fmin(__CLC_GENTYPE x, half y) {
23 return fmin(x, (__CLC_GENTYPE)((__CLC_SCALAR_GENTYPE)y));
H A Dfmin.cl5 _CLC_DEFINE_BINARY_BUILTIN(float, fmin, __builtin_fminf, float, float);
11 _CLC_DEFINE_BINARY_BUILTIN(double, fmin, __builtin_fmin, double, double);
18 _CLC_DEF _CLC_OVERLOAD half fmin(half x, half y)
26 _CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, fmin, half, half)
30 #define __CLC_BODY <fmin.inc>
/llvm-project-15.0.7/libclc/r600/lib/math/
H A Dfmin.cl6 _CLC_DEF _CLC_OVERLOAD float fmin(float x, float y)
9 * Otherwise fmin instruction flushes the values for comparison,
15 _CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, fmin, float, float)
21 _CLC_DEF _CLC_OVERLOAD double fmin(double x, double y)
25 _CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, fmin, double, double)
29 #define __CLC_BODY <../../../generic/lib/math/fmin.inc>
/llvm-project-15.0.7/llvm/test/MC/VE/
H A DFMAXMIN.s14 # CHECK-INST: fmin.d %s11, 63, (63)1
16 fmin.d %s11, 63, (63)1
18 # CHECK-INST: fmin.s %s11, -64, %s22
20 fmin.s %s11, -64, %s22
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvector-reduce-fmin-nnan.ll464 declare float @llvm.vector.reduce.fmin.v1f32(<1 x float>)
465 declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>)
466 declare float @llvm.vector.reduce.fmin.v3f32(<3 x float>)
467 declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
468 declare float @llvm.vector.reduce.fmin.v8f32(<8 x float>)
469 declare float @llvm.vector.reduce.fmin.v16f32(<16 x float>)
471 declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
472 declare double @llvm.vector.reduce.fmin.v4f64(<4 x double>)
473 declare double @llvm.vector.reduce.fmin.v8f64(<8 x double>)
474 declare double @llvm.vector.reduce.fmin.v16f64(<16 x double>)
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dneon-max-min.s85 fmin v10.4h, v15.4h, v22.4h
86 fmin v10.8h, v15.8h, v22.8h
87 fmin v10.2s, v15.2s, v22.2s
88 fmin v3.4s, v5.4s, v6.4s
89 fmin v17.2d, v13.2d, v2.2d
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dvecreduce-fmin-legalization.ll5 declare half @llvm.vector.reduce.fmin.v1f16(<1 x half> %a)
6 declare float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a)
7 declare double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)
8 declare fp128 @llvm.vector.reduce.fmin.v1f128(<1 x fp128> %a)
10 declare half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
11 declare half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)
12 declare float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
13 declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
14 declare float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)
20 %b = call nnan half @llvm.vector.reduce.fmin.v1f16(<1 x half> %a)
[all …]
H A Dsve-fixed-length-fp-reduce.ll1112 declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>)
1113 declare half @llvm.vector.reduce.fmin.v8f16(<8 x half>)
1114 declare half @llvm.vector.reduce.fmin.v16f16(<16 x half>)
1115 declare half @llvm.vector.reduce.fmin.v32f16(<32 x half>)
1116 declare half @llvm.vector.reduce.fmin.v64f16(<64 x half>)
1117 declare half @llvm.vector.reduce.fmin.v128f16(<128 x half>)
1119 declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>)
1120 declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
1121 declare float @llvm.vector.reduce.fmin.v8f32(<8 x float>)
1122 declare float @llvm.vector.reduce.fmin.v16f32(<16 x float>)
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/RISCV/
H A Dreduce-scalable-fp.ll317 declare half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half>)
346 declare half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half>)
357 declare half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half>)
368 declare half @llvm.vector.reduce.fmin.nxv64f16(<vscale x 64 x half>)
379 declare float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float>)
408 declare float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float>)
419 declare float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float>)
430 declare float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float>)
441 declare double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double>)
470 declare double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double>)
[all …]
/llvm-project-15.0.7/compiler-rt/lib/builtins/hexagon/
H A Ddfminmax.S28 .global fmin
29 .type fmin,@function
38 fmin: label
/llvm-project-15.0.7/libc/src/math/generic/
H A Dfmin.cpp15 LLVM_LIBC_FUNCTION(double, fmin, (double x, double y)) {
16 return fputil::fmin(x, y);
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dclamp-fmed3-const-combine.ll28 ; %fmin is known non-SNaN because fmin inputs are fcanonicalized
37 %fmin = call float @llvm.minnum.f32(float %a, float 10.0)
38 %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmin, float 0.0, float 1.0)
97 %fmin = call float @llvm.minnum.f32(float %a, float 10.0)
98 %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmin, float 0.0, float 1.0)
H A Dllvm.amdgcn.ds.fmin.ll39 …%ret = call float @llvm.amdgcn.ds.fmin(float addrspace(3)* %ptr, float %val, i32 0, i32 0, i1 fals…
76 …%ret = call float @llvm.amdgcn.ds.fmin(float addrspace(3)* %gep, float %val, i32 0, i32 0, i1 fals…
108 …%unused = call float @llvm.amdgcn.ds.fmin(float addrspace(3)* %ptr, float %val, i32 0, i32 0, i1 f…
141 …%unused = call float @llvm.amdgcn.ds.fmin(float addrspace(3)* %gep, float %val, i32 0, i32 0, i1 f…
168 …%ret = call float @llvm.amdgcn.ds.fmin(float addrspace(3)* %ptr, float %val, i32 0, i32 0, i1 fals…
196 …%ret = call float @llvm.amdgcn.ds.fmin(float addrspace(3)* %gep, float %val, i32 0, i32 0, i1 fals…
223 …%ret = call float @llvm.amdgcn.ds.fmin(float addrspace(3)* %ptr, float %val, i32 0, i32 0, i1 fals…
251 …%ret = call float @llvm.amdgcn.ds.fmin(float addrspace(3)* %gep, float %val, i32 0, i32 0, i1 fals…
278 …%ret = call float @llvm.amdgcn.ds.fmin(float addrspace(3)* %ptr, float %val, i32 0, i32 0, i1 true)
282 declare float @llvm.amdgcn.ds.fmin(float addrspace(3)* nocapture, float, i32 immarg, i32 immarg, i1…
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/
H A Dreduce-minmax.ll176 %V2f16 = call half @llvm.vector.reduce.fmin.v2f16(<2 x half> undef)
177 %V4f16 = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> undef)
307 declare half @llvm.vector.reduce.fmin.v2f16(<2 x half>)
308 declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>)
309 declare half @llvm.vector.reduce.fmin.v8f16(<8 x half>)
310 declare half @llvm.vector.reduce.fmin.v16f16(<16 x half>)
311 declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>)
312 declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
313 declare float @llvm.vector.reduce.fmin.v8f32(<8 x float>)
314 declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvecreduce-fmin-legalization-soft-float.ll4 declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>)
5 declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
6 declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
7 declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128>)
51 %b = call fast half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
80 %b = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)
108 %b = call fast double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)
175 %b = call fast fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
/llvm-project-15.0.7/llvm/test/Bitcode/
H A Dupgrade-vecreduce-intrinsics.ll33 define float @fmin(<4 x float> %in) {
34 ; CHECK-LABEL: @fmin
35 ; CHECK: %res = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %in)
36 %res = call float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %in)
100 declare float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float>)
101 ; CHECK: declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
/llvm-project-15.0.7/llvm/test/Assembler/
H A Datomic.ll56 ; CHECK: atomicrmw fmin float* %x, float 1.000000e+00 seq_cst
57 atomicrmw fmin float* %x, float 1.0 seq_cst
59 ; CHECK: atomicrmw volatile fmin float* %x, float 1.000000e+00 seq_cst
60 atomicrmw volatile fmin float* %x, float 1.0 seq_cst
/llvm-project-15.0.7/llvm/test/Transforms/LowerAtomic/
H A Datomic-load.ll72 define float @fmin() {
73 ; CHECK-LABEL: @fmin(
75 %j = atomicrmw fmin float* %i, float 42.0 monotonic

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