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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A D2008-07-19-movups-spills.ll110 fmul <4 x float> %1, %1 ; <<4 x float>>:33 [#uses=1]
111 fmul <4 x float> %33, %2 ; <<4 x float>>:34 [#uses=1]
112 fmul <4 x float> %34, %3 ; <<4 x float>>:35 [#uses=1]
113 fmul <4 x float> %35, %4 ; <<4 x float>>:36 [#uses=1]
114 fmul <4 x float> %36, %5 ; <<4 x float>>:37 [#uses=1]
115 fmul <4 x float> %37, %6 ; <<4 x float>>:38 [#uses=1]
116 fmul <4 x float> %38, %7 ; <<4 x float>>:39 [#uses=1]
117 fmul <4 x float> %39, %8 ; <<4 x float>>:40 [#uses=1]
118 fmul <4 x float> %40, %9 ; <<4 x float>>:41 [#uses=1]
142 fmul <4 x float> %2, %2 ; <<4 x float>>:65 [#uses=1]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dscratch-simple.ll81 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
82 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
132 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
133 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
178 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
179 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
207 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
208 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
255 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
256 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
[all …]
H A Dschedule-regpressure-limit3.ll24 %tmp7 = tail call float @llvm.fmuladd.f32(float %tmp2, float %tmp4, float %tmp6)
31 %tmp14 = tail call float @llvm.fmuladd.f32(float %tmp9, float %tmp11, float %tmp13)
38 %tmp21 = tail call float @llvm.fmuladd.f32(float %tmp16, float %tmp18, float %tmp20)
45 %tmp28 = tail call float @llvm.fmuladd.f32(float %tmp23, float %tmp25, float %tmp27)
52 %tmp35 = tail call float @llvm.fmuladd.f32(float %tmp30, float %tmp32, float %tmp34)
59 %tmp42 = tail call float @llvm.fmuladd.f32(float %tmp37, float %tmp39, float %tmp41)
66 %tmp49 = tail call float @llvm.fmuladd.f32(float %tmp44, float %tmp46, float %tmp48)
73 %tmp56 = tail call float @llvm.fmuladd.f32(float %tmp51, float %tmp53, float %tmp55)
80 %tmp63 = tail call float @llvm.fmuladd.f32(float %tmp58, float %tmp60, float %tmp62)
87 %tmp70 = tail call float @llvm.fmuladd.f32(float %tmp65, float %tmp67, float %tmp69)
[all …]
H A Dschedule-ilp.ll13 %tmp7 = tail call float @llvm.fmuladd.f32(float %tmp2, float %tmp4, float %tmp6)
20 %tmp14 = tail call float @llvm.fmuladd.f32(float %tmp9, float %tmp11, float %tmp13)
27 %tmp21 = tail call float @llvm.fmuladd.f32(float %tmp16, float %tmp18, float %tmp20)
34 %tmp28 = tail call float @llvm.fmuladd.f32(float %tmp23, float %tmp25, float %tmp27)
41 %tmp35 = tail call float @llvm.fmuladd.f32(float %tmp30, float %tmp32, float %tmp34)
48 %tmp42 = tail call float @llvm.fmuladd.f32(float %tmp37, float %tmp39, float %tmp41)
55 %tmp49 = tail call float @llvm.fmuladd.f32(float %tmp44, float %tmp46, float %tmp48)
62 %tmp56 = tail call float @llvm.fmuladd.f32(float %tmp51, float %tmp53, float %tmp55)
69 %tmp63 = tail call float @llvm.fmuladd.f32(float %tmp58, float %tmp60, float %tmp62)
76 %tmp70 = tail call float @llvm.fmuladd.f32(float %tmp65, float %tmp67, float %tmp69)
[all …]
H A Dschedule-regpressure-limit.ll16 %tmp7 = tail call float @llvm.fmuladd.f32(float %tmp2, float %tmp4, float %tmp6)
23 %tmp14 = tail call float @llvm.fmuladd.f32(float %tmp9, float %tmp11, float %tmp13)
30 %tmp21 = tail call float @llvm.fmuladd.f32(float %tmp16, float %tmp18, float %tmp20)
37 %tmp28 = tail call float @llvm.fmuladd.f32(float %tmp23, float %tmp25, float %tmp27)
44 %tmp35 = tail call float @llvm.fmuladd.f32(float %tmp30, float %tmp32, float %tmp34)
51 %tmp42 = tail call float @llvm.fmuladd.f32(float %tmp37, float %tmp39, float %tmp41)
58 %tmp49 = tail call float @llvm.fmuladd.f32(float %tmp44, float %tmp46, float %tmp48)
65 %tmp56 = tail call float @llvm.fmuladd.f32(float %tmp51, float %tmp53, float %tmp55)
72 %tmp63 = tail call float @llvm.fmuladd.f32(float %tmp58, float %tmp60, float %tmp62)
79 %tmp70 = tail call float @llvm.fmuladd.f32(float %tmp65, float %tmp67, float %tmp69)
[all …]
H A Dschedule-regpressure-limit2.ll198 %res.0 = tail call float @llvm.fmuladd.f32(float %a.0, float %b.0, float %c.0)
199 %res.1 = tail call float @llvm.fmuladd.f32(float %a.1, float %b.1, float %c.1)
200 %res.2 = tail call float @llvm.fmuladd.f32(float %a.2, float %b.2, float %c.2)
201 %res.3 = tail call float @llvm.fmuladd.f32(float %a.3, float %b.3, float %c.3)
202 %res.4 = tail call float @llvm.fmuladd.f32(float %a.4, float %b.4, float %c.4)
203 %res.5 = tail call float @llvm.fmuladd.f32(float %a.5, float %b.5, float %c.5)
204 %res.6 = tail call float @llvm.fmuladd.f32(float %a.6, float %b.6, float %c.6)
205 %res.7 = tail call float @llvm.fmuladd.f32(float %a.7, float %b.7, float %c.7)
206 %res.8 = tail call float @llvm.fmuladd.f32(float %a.8, float %b.8, float %c.8)
207 %res.9 = tail call float @llvm.fmuladd.f32(float %a.9, float %b.9, float %c.9)
[all …]
H A Dsoft-clause-exceeds-register-budget.ll342 %i141 = tail call float @llvm.fmuladd.f32(float %i9, float %i13, float %i140)
346 %i145 = tail call float @llvm.fmuladd.f32(float %i9, float %i17, float %i144)
350 %i149 = tail call float @llvm.fmuladd.f32(float %i9, float %i21, float %i148)
354 %i153 = tail call float @llvm.fmuladd.f32(float %i9, float %i25, float %i152)
358 %i157 = tail call float @llvm.fmuladd.f32(float %i9, float %i29, float %i156)
362 %i161 = tail call float @llvm.fmuladd.f32(float %i9, float %i33, float %i160)
366 %i165 = tail call float @llvm.fmuladd.f32(float %i9, float %i37, float %i164)
370 %i169 = tail call float @llvm.fmuladd.f32(float %i9, float %i41, float %i168)
374 %i173 = tail call float @llvm.fmuladd.f32(float %i9, float %i45, float %i172)
562 declare float @llvm.fmuladd.f32(float, float, float) #0
[all …]
H A Dps-shader-arg-count.ll6 …float> } @_amdgpu_ps_1_arg(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2…
16 …float> } @_amdgpu_ps_3_arg(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2…
56 …float>, <4 x float>, <4 x float>, <4 x float> } @_amdgpu_ps_all_arg(i32 inreg %arg, i32 inreg %arg…
91 …%ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } undef, <4 x float>…
96 ret { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res
102 …float>, <4 x float>, <4 x float>, <4 x float> } @_amdgpu_ps_all_arg_extra_unused(i32 inreg %arg, i…
142 ret { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res
148 …float>, <4 x float>, <4 x float>, <4 x float> } @_amdgpu_ps_all_arg_extra(i32 inreg %arg, i32 inre…
191 ret { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res
318 ret { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A D2009-11-13-ScavengerAssert2.ll25 %3 = load float, float* %2, align 4 ; <float> [#uses=1]
29 %7 = load float, float* %6, align 4 ; <float> [#uses=1]
32 %10 = load float, float* %9, align 4 ; <float> [#uses=1]
35 %13 = load float, float* %12, align 4 ; <float> [#uses=1]
37 %15 = load float, float* undef, align 4 ; <float> [#uses=1]
46 store float %18, float* undef
48 store float %20, float* %24
49 store float %23, float* undef
55 %30 = load float, float* null, align 4 ; <float> [#uses=2]
105 %80 = select i1 %66, float %48, float %65 ; <float> [#uses=1]
[all …]
H A D2009-11-07-SubRegAsmPrinting.ll9 %0 = load float, float* null, align 4 ; <float> [#uses=2]
21 %10 = load float, float* undef, align 8 ; <float> [#uses=3]
33 %22 = load float, float* undef, align 8 ; <float> [#uses=1]
36 %25 = load float, float* undef, align 8 ; <float> [#uses=2]
52 store float %12, float* undef, align 8
53 store float %17, float* undef, align 4
54 store float %21, float* undef, align 8
55 store float %27, float* undef, align 8
56 store float %29, float* undef, align 4
59 store float %12, float* null, align 8
[all …]
H A D2009-11-13-VRRewriterCrash.ll38 store float %14, float* undef
40 store float 0.000000e+00, float* %15
46 %21 = load float, float* %1, align 4 ; <float> [#uses=2]
47 %22 = load float, float* %3, align 4 ; <float> [#uses=2]
48 %23 = load float, float* undef, align 4 ; <float> [#uses=2]
49 %24 = load float, float* %4, align 4 ; <float> [#uses=2]
62 %37 = load float, float* %6, align 4 ; <float> [#uses=2]
63 %38 = load float, float* %7, align 4 ; <float> [#uses=2]
94 %69 = select i1 undef, float %36, float %52 ; <float> [#uses=1]
95 %70 = select i1 undef, float %69, float %68 ; <float> [#uses=1]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/X86/
H A Dx86-sse-inseltpoison.ll90 define float @test_add_ss_0(float %a, float %b) {
108 define float @test_add_ss_1(float %a, float %b) {
133 define float @test_sub_ss_0(float %a, float %b) {
151 define float @test_sub_ss_2(float %a, float %b) {
176 define float @test_mul_ss_0(float %a, float %b) {
194 define float @test_mul_ss_3(float %a, float %b) {
219 define float @test_div_ss_0(float %a, float %b) {
237 define float @test_div_ss_1(float %a, float %b) {
274 define float @test_min_ss_0(float %a, float %b) {
295 define float @test_min_ss_2(float %a, float %b) {
[all …]
H A Dx86-sse.ll90 define float @test_add_ss_0(float %a, float %b) {
108 define float @test_add_ss_1(float %a, float %b) {
133 define float @test_sub_ss_0(float %a, float %b) {
151 define float @test_sub_ss_2(float %a, float %b) {
176 define float @test_mul_ss_0(float %a, float %b) {
194 define float @test_mul_ss_3(float %a, float %b) {
219 define float @test_div_ss_0(float %a, float %b) {
237 define float @test_div_ss_1(float %a, float %b) {
274 define float @test_min_ss_0(float %a, float %b) {
295 define float @test_min_ss_2(float %a, float %b) {
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A D2003-05-28-ManyArgs.ll46 … float, float, float, float, float, float, float, float, float, float } ; <{ i32, float, float, f…
52 …2, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, fl…
121 …float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float…
123 …float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float…
125 …float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float…
127 …float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float…
129 …float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float…
131 …float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float…
133 …float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float…
135 …float, float, float, float, float, float, float, float, float, float }, { i32, float, float, float…
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/
H A Dcubetc.ll4 declare float @llvm.amdgcn.cubetc(float, float, float)
58 %p3p4p5 = call float @llvm.amdgcn.cubetc(float +3.0, float +4.0, float +5.0)
60 %p3p5p4 = call float @llvm.amdgcn.cubetc(float +3.0, float +5.0, float +4.0)
62 %p4p3p5 = call float @llvm.amdgcn.cubetc(float +4.0, float +3.0, float +5.0)
64 %p4p5p3 = call float @llvm.amdgcn.cubetc(float +4.0, float +5.0, float +3.0)
66 %p5p3p4 = call float @llvm.amdgcn.cubetc(float +5.0, float +3.0, float +4.0)
68 %p5p4p3 = call float @llvm.amdgcn.cubetc(float +5.0, float +4.0, float +3.0)
70 %p3p4n5 = call float @llvm.amdgcn.cubetc(float +3.0, float +4.0, float -5.0)
72 %p3p5n4 = call float @llvm.amdgcn.cubetc(float +3.0, float +5.0, float -4.0)
74 %p4p3n5 = call float @llvm.amdgcn.cubetc(float +4.0, float +3.0, float -5.0)
[all …]
H A Dcubeid.ll4 declare float @llvm.amdgcn.cubeid(float, float, float)
58 %p3p4p5 = call float @llvm.amdgcn.cubeid(float +3.0, float +4.0, float +5.0)
60 %p3p5p4 = call float @llvm.amdgcn.cubeid(float +3.0, float +5.0, float +4.0)
62 %p4p3p5 = call float @llvm.amdgcn.cubeid(float +4.0, float +3.0, float +5.0)
64 %p4p5p3 = call float @llvm.amdgcn.cubeid(float +4.0, float +5.0, float +3.0)
66 %p5p3p4 = call float @llvm.amdgcn.cubeid(float +5.0, float +3.0, float +4.0)
68 %p5p4p3 = call float @llvm.amdgcn.cubeid(float +5.0, float +4.0, float +3.0)
70 %p3p4n5 = call float @llvm.amdgcn.cubeid(float +3.0, float +4.0, float -5.0)
72 %p3p5n4 = call float @llvm.amdgcn.cubeid(float +3.0, float +5.0, float -4.0)
74 %p4p3n5 = call float @llvm.amdgcn.cubeid(float +4.0, float +3.0, float -5.0)
[all …]
H A Dcubema.ll4 declare float @llvm.amdgcn.cubema(float, float, float)
58 %p3p4p5 = call float @llvm.amdgcn.cubema(float +3.0, float +4.0, float +5.0)
60 %p3p5p4 = call float @llvm.amdgcn.cubema(float +3.0, float +5.0, float +4.0)
62 %p4p3p5 = call float @llvm.amdgcn.cubema(float +4.0, float +3.0, float +5.0)
64 %p4p5p3 = call float @llvm.amdgcn.cubema(float +4.0, float +5.0, float +3.0)
66 %p5p3p4 = call float @llvm.amdgcn.cubema(float +5.0, float +3.0, float +4.0)
68 %p5p4p3 = call float @llvm.amdgcn.cubema(float +5.0, float +4.0, float +3.0)
70 %p3p4n5 = call float @llvm.amdgcn.cubema(float +3.0, float +4.0, float -5.0)
72 %p3p5n4 = call float @llvm.amdgcn.cubema(float +3.0, float +5.0, float -4.0)
74 %p4p3n5 = call float @llvm.amdgcn.cubema(float +4.0, float +3.0, float -5.0)
[all …]
H A Dcubesc.ll4 declare float @llvm.amdgcn.cubesc(float, float, float)
58 %p3p4p5 = call float @llvm.amdgcn.cubesc(float +3.0, float +4.0, float +5.0)
60 %p3p5p4 = call float @llvm.amdgcn.cubesc(float +3.0, float +5.0, float +4.0)
62 %p4p3p5 = call float @llvm.amdgcn.cubesc(float +4.0, float +3.0, float +5.0)
64 %p4p5p3 = call float @llvm.amdgcn.cubesc(float +4.0, float +5.0, float +3.0)
66 %p5p3p4 = call float @llvm.amdgcn.cubesc(float +5.0, float +3.0, float +4.0)
68 %p5p4p3 = call float @llvm.amdgcn.cubesc(float +5.0, float +4.0, float +3.0)
70 %p3p4n5 = call float @llvm.amdgcn.cubesc(float +3.0, float +4.0, float -5.0)
72 %p3p5n4 = call float @llvm.amdgcn.cubesc(float +3.0, float +5.0, float -4.0)
74 %p4p3n5 = call float @llvm.amdgcn.cubesc(float +4.0, float +3.0, float -5.0)
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dfminmax-folds.ll4 declare float @llvm.minnum.f32(float, float)
5 declare float @llvm.maxnum.f32(float, float)
6 declare float @llvm.minimum.f32(float, float)
7 declare float @llvm.maximum.f32(float, float)
8 declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>)
9 declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>)
691 define float @minnum_z_minnum_x_y(float %x, float %y, float %z) {
704 define float @minnum_x_y_minnum_z(float %x, float %y, float %z) {
785 define float @maxnum_z_maxnum_x_y(float %x, float %y, float %z) {
798 define float @maxnum_x_y_maxnum_z(float %x, float %y, float %z) {
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dhorizontal-list.ll16 ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* bitcast ([20 x float]* @arr to <4 x …
17 ; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, <4 x float>* bitcast ([20 x float]* @arr1 to <4 x…
45 …%1 = load float, float* getelementptr inbounds ([20 x float], [20 x float]* @arr, i64 0, i64 0), a…
46 …%2 = load float, float* getelementptr inbounds ([20 x float], [20 x float]* @arr1, i64 0, i64 0), …
49 …%3 = load float, float* getelementptr inbounds ([20 x float], [20 x float]* @arr, i64 0, i64 1), a…
50 …%4 = load float, float* getelementptr inbounds ([20 x float], [20 x float]* @arr1, i64 0, i64 1), …
53 …%5 = load float, float* getelementptr inbounds ([20 x float], [20 x float]* @arr, i64 0, i64 2), a…
54 …%6 = load float, float* getelementptr inbounds ([20 x float], [20 x float]* @arr1, i64 0, i64 2), …
57 …%7 = load float, float* getelementptr inbounds ([20 x float], [20 x float]* @arr, i64 0, i64 3), a…
58 …%8 = load float, float* getelementptr inbounds ([20 x float], [20 x float]* @arr1, i64 0, i64 3), …
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dlarge-number-of-preds.ll6 @g0 = external global void (float*, i32, i32, float*, float*)**
9 define void @f0(float* nocapture %a0, float* nocapture %a1, float* %a2) #0 {
15 %v3 = load float, float* %a0, align 4, !tbaa !0
17 store float %v3, float* %v4, align 4, !tbaa !0
19 store float %v3, float* %v5, align 16, !tbaa !0
21 %v7 = load float, float* %v6, align 4, !tbaa !0
23 store float %v7, float* %v8, align 16, !tbaa !0
25 store float %v7, float* %v9, align 4, !tbaa !0
221 …%v137 = load void (float*, i32, i32, float*, float*)**, void (float*, i32, i32, float*, float*)***…
222 …%v138 = load void (float*, i32, i32, float*, float*)*, void (float*, i32, i32, float*, float*)** %…
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopReroll/
H A Dbasic32iters.ll5 ; void goo32(float alpha, float *a, float *b) {
43 define void @goo32(float %alpha, float* %a, float* readonly %b) #0 {
50 %0 = load float, float* %arrayidx, align 4
53 %1 = load float, float* %arrayidx2, align 4
55 store float %add, float* %arrayidx2, align 4
58 %3 = load float, float* %arrayidx5, align 4
61 %4 = load float, float* %arrayidx9, align 4
66 %6 = load float, float* %arrayidx13, align 4
69 %7 = load float, float* %arrayidx17, align 4
74 %9 = load float, float* %arrayidx21, align 4
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dmaximum.ll4 declare float @llvm.maximum.f32(float, float)
5 declare <2 x float> @llvm.maximum.v2f32(<2 x float>, <2 x float>)
6 declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>)
15 %x = call float @llvm.maximum.f32(float 1.0, float 2.0)
23 %x = call float @llvm.maximum.f32(float 2.0, float 1.0)
55 %x = call float @llvm.maximum.f32(float 0.0, float 0.0)
63 %x = call float @llvm.maximum.f32(float 0.0, float -0.0)
85 ; CHECK-NEXT: ret <4 x float> <float 2.000000e+00, float 8.000000e+00, float 1.000000e+01, float…
87 …ll <4 x float> @llvm.maximum.v4f32(<4 x float> <float 1.0, float 8.0, float 3.0, float 9.0>, <4 x …
224 %z = call <2 x float> @llvm.maximum.v2f32(<2 x float> %y, <2 x float><float 1.0, float 1.0>)
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Daccelerate-vector-functions-inseltpoison.ll8 declare float @llvm.sin.f32(float)
11 define <4 x float> @int_sin_4x(<4 x float>* %a) {
37 %0 = load <4 x float>, <4 x float>* %a, align 16
55 define <4 x float> @ceil_4x(<4 x float>* %a) {
71 %1 = tail call fast float @ceilf(float %vecext)
87 define <4 x float> @fabs_4x(<4 x float>* %a) {
147 define <4 x float> @floor_4x(<4 x float>* %a) {
177 define <4 x float> @sqrt_4x(<4 x float>* %a) {
207 define <4 x float> @exp_4x(<4 x float>* %a) {
290 define <4 x float> @log_4x(<4 x float>* %a) {
[all …]
H A Daccelerate-vector-functions.ll8 declare float @llvm.sin.f32(float)
11 define <4 x float> @int_sin_4x(<4 x float>* %a) {
37 %0 = load <4 x float>, <4 x float>* %a, align 16
55 define <4 x float> @ceil_4x(<4 x float>* %a) {
71 %1 = tail call fast float @ceilf(float %vecext)
87 define <4 x float> @fabs_4x(<4 x float>* %a) {
116 declare float @llvm.fabs.f32(float)
147 define <4 x float> @floor_4x(<4 x float>* %a) {
177 define <4 x float> @sqrt_4x(<4 x float>* %a) {
207 define <4 x float> @exp_4x(<4 x float>* %a) {
[all …]

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