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/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dgfx10_asm_dpp8.s255 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:0
258 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
315 v_exp_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
318 v_log_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
321 v_rcp_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
327 v_rsq_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
333 v_sin_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
336 v_cos_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
339 v_not_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
372 v_rcp_f16_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
[all …]
H A Dgfx11_asm_dpp8.s253 v_mov_b32 v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:0
256 v_mov_b32 v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
313 v_exp_f32 v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
316 v_log_f32 v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
319 v_rcp_f32 v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
325 v_rsq_f32 v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
331 v_sin_f32 v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
334 v_cos_f32 v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
337 v_not_b32 v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
370 v_rcp_f16 v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
[all …]
H A Dgfx11_asm_vop3_dpp8.s285 v_and_b16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
294 v_and_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
474 v_bfm_b32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
483 v_bfrev_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
516 v_cls_i32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
4437 v_ffbh_i32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
4446 v_ffbh_u32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
4455 v_ffbl_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
6084 v_mov_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
6267 v_not_b16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
[all …]
H A Dgfx11_asm_dpp16.s340 v_mov_b32 v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:0
343 v_mov_b32 v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
400 v_exp_f32 v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
403 v_log_f32 v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
406 v_rcp_f32 v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
412 v_rsq_f32 v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
418 v_sin_f32 v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
421 v_cos_f32 v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
424 v_not_b32 v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
457 v_rcp_f16 v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
[all …]
H A Dgfx10_asm_dpp16.s372 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:0
375 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
432 v_exp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
435 v_log_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
438 v_rcp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
444 v_rsq_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
450 v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
453 v_cos_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
456 v_not_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
489 v_rcp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
[all …]
H A Dgfx11_asm_vopc_dpp.s12 v_cmp_le_u16_dpp v1, v2 dpp8:[7,7,7,3,4,4,6,7] fi:1
35 v_cmp_lt_u16_dpp vcc, v1, v2 dpp8:[7,6,5,3,4,2,1,0] fi:1
41 v_cmp_class_f16_dpp vcc, v1, v2 dpp8:[7,6,5,3,4,2,1,0] fi:1
47 v_cmpx_f_i32_dpp v0, v2 dpp8:[7,6,5,3,4,2,1,0] fi:1
71 v_cmp_gt_i32_e64_dpp s10, v1, v50 dpp8:[0,1,2,3,4,5,6,7] fi:1
75 v_cmp_ngt_f32_e64_dpp s10, -v1, v2 dpp8:[0,1,2,3,4,5,6,7] fi:1
81 v_cmp_f_f32_e64_dpp s[10:11], v1, v2 dpp8:[0,1,2,3,4,5,6,7] fi:1
109 v_cmpx_eq_i16_e64_dpp v5, v25 dpp8:[0,1,6,3,4,5,6,7] fi:1
112 v_cmpx_ge_i32_e64_dpp v0, v3 dpp8:[0,1,6,3,4,5,6,7] fi:1
117 v_cmpx_class_f32_e64_dpp v1, v20 dpp8:[0,1,6,3,4,5,6,7] fi:1
[all …]
H A Dgfx11_asm_dpp.s16 v_ctz_i32_b32_e64_dpp v199, v1 dpp8:[0,0,2,3,4,4,6,7] fi:1
20 v_xnor_b32_e64_dpp v8, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
23 v_add_nc_u32_e64_dpp v60, v61, v62 dpp8:[7,6,5,3,4,2,1,0] fi:1
34 v_add_co_ci_u32_e64_dpp v0, s2, v1, v2, s1 clamp dpp8:[7,6,5,3,4,2,1,0] fi:1
46 v_sub_co_ci_u32_e64_dpp v0, vcc, v1, v2, s[2:3] dpp8:[7,6,5,3,4,2,1,0] fi:1
58 v_maxmin_f32_e64_dpp v0, v1, v2, v3 div:2 dpp8:[0,1,2,3,4,5,6,7] fi:1
95 v_fma_mix_f32 v0, v1, v2, v3 clamp dpp8:[2,2,2,2,4,4,4,4] fi:1
118 v_sat_pk_u8_i16_e64_dpp v0, v2 row_mirror bank_mask:0x2 fi:1
140 v_cndmask_b32_e64_dpp v202, v1, v2, s1 quad_perm:[2,3,0,0] fi:1
154 v_dot2c_f32_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
[all …]
H A Dgfx11_asm_vop3_dpp16.s42 v_add3_u32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
676 v_and_b16_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
718 v_and_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1054 v_bfm_b32_e64_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1096 v_bfrev_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1222 v_cls_i32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1264 v_clz_i32_u32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
12988 v_ffbh_i32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
15928 v_mov_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
16474 v_not_b16_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
[all …]
H A Dgfx1011_dlops.s38 v_dot2c_f32_f16 v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1
44 v_dot2c_f32_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
53 v_dot4c_i32_i8 v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1
59 v_dot4c_i32_i8 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Dproperty-complex.m26 printf("im0: %.2f + %.2fi\n", __real iv0, __imag iv0);
30 printf("setIm0: %.2f + %.2fi\n", __real a0, __imag a0);
35 printf("p0: %.2f + %.2fi\n", __real iv0, __imag iv0);
39 printf("setP0: %.2f + %.2fi\n", __real a0, __imag a0);
54 printf("l0: %.2f + %.2fi\n", __real l0, __imag l0);
55 printf("l1: %.2f + %.2fi\n", __real l1, __imag l1);
56 printf("l2: %.2f + %.2fi\n", __real l2, __imag l2);
57 printf("l3: %.2f + %.2fi\n", __real l3, __imag l3);
58 printf("l4: %.2f + %.2fi\n", __real l4, __imag l4);
59 printf("l5: %.2f + %.2fi\n", __real l5, __imag l5);
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx10_dasm_dpp8.txt253 # GFX10: v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x02,0x0a,0x7e,0x01,0x8…
310 # GFX10: v_exp_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x4a,0x0a,0x7e,0x01,0x8…
313 # GFX10: v_log_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x4e,0x0a,0x7e,0x01,0x8…
316 # GFX10: v_rcp_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x54,0x0a,0x7e,0x01,0x8…
322 # GFX10: v_rsq_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x5c,0x0a,0x7e,0x01,0x8…
328 # GFX10: v_sin_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x6a,0x0a,0x7e,0x01,0x8…
331 # GFX10: v_cos_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x6c,0x0a,0x7e,0x01,0x8…
334 # GFX10: v_not_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x6e,0x0a,0x7e,0x01,0x8…
367 # GFX10: v_rcp_f16_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0xa8,0x0a,0x7e,0x01,0x8…
373 # GFX10: v_rsq_f16_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0xac,0x0a,0x7e,0x01,0x8…
[all …]
H A Dgfx10_dasm_dpp16.txt73 # GFX10: v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa…
323 # W32: v_cndmask_b32_dpp v0, v1, v2, vcc_lo dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x04,0x0…
324 # W64: v_cndmask_b32_dpp v0, v1, v2, vcc dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x04,0x00,0…
366 # GFX10: v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa…
423 # GFX10: v_exp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa…
426 # GFX10: v_log_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa…
429 # GFX10: v_rcp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa…
435 # GFX10: v_rsq_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa…
441 # GFX10: v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa…
444 # GFX10: v_cos_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa…
[all …]
/llvm-project-15.0.7/clang/test/OpenMP/
H A Dparallel_for_misc_messages.c307 for (float fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
308 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
312 for (double fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
313 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
H A Dtarget_parallel_for_misc_messages.c307 for (float fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
308 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
312 for (double fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
313 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
H A Dfor_misc_messages.c387 for (float fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
388 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
393 for (double fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
394 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
H A Dtaskloop_misc_messages.c366 for (float fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
367 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
372 for (double fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
373 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
H A Dtarget_teams_distribute_misc_messages.c308 for (float fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
309 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
313 for (double fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
314 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
H A Dmaster_taskloop_misc_messages.c366 for (float fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
367 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
372 for (double fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
373 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
H A Dtarget_teams_distribute_parallel_for_misc_messages.c308 for (float fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
309 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
313 for (double fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
314 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
H A Dparallel_master_taskloop_misc_messages.c369 for (float fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
370 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
375 for (double fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
376 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
H A Dtaskloop_simd_misc_messages.c371 for (float fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
372 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
377 for (double fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
378 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
H A Dmaster_taskloop_simd_misc_messages.c371 for (float fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
372 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
377 for (double fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
378 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
H A Dtarget_teams_distribute_parallel_for_simd_misc_messages.c314 for (float fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
315 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
319 for (double fi = 0; fi < 10.0; fi++) { in test_loop_messages() local
320 c[(int)fi] = a[(int)fi] + b[(int)fi]; in test_loop_messages()
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dmcm-1.ll10 $fi = comdat any
13 @fi = global i32 0, align 4, comdat($fi)
14 @gi = global i32 0, align 4, comdat($fi)
27 %1 = load i32, i32* @fi, align 4
47 ; CHECK-NEXT: .tc fi[TC],fi
/llvm-project-15.0.7/third-party/benchmark/
H A D.travis.yml153 fi
158 fi
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