| /llvm-project-15.0.7/llvm/test/MC/RISCV/ |
| H A D | rvf-user-csr-names.s | 55 # fcsr
57 # CHECK-INST: csrrs t1, fcsr, zero
60 # CHECK-INST-ALIAS-NO-F: csrr t1, fcsr
62 # CHECK-INST: csrrs t2, fcsr, zero
65 # CHECK-INST-ALIAS-NO-F: csrr t2, fcsr
67 csrrs t1, fcsr, zero
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| H A D | csr-aliases.s | 40 # CHECK-INST: csrrs t0, fcsr, zero
43 # CHECK-EXT-F-OFF: csrr t0, fcsr
46 # CHECK-INST: csrrw t1, fcsr, t2
49 # CHECK-EXT-F-OFF: csrrw t1, fcsr, t2
52 # CHECK-INST: csrrw zero, fcsr, t2
55 # CHECK-EXT-F-OFF: csrw fcsr, t2
58 # CHECK-INST: csrrw zero, fcsr, t2
61 # CHECK-EXT-F-OFF: csrw fcsr, t2
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| H A D | rvf-aliases-valid.s | 52 # CHECK-INST: csrrs t0, fcsr, zero
55 # CHECK-INST: csrrw t1, fcsr, t2
58 # CHECK-INST: csrrw zero, fcsr, t3
64 # CHECK-INST: csrrs t4, fcsr, zero
67 # CHECK-INST: csrrw t5, fcsr, t6
70 # CHECK-INST: csrrw zero, fcsr, s0
|
| /llvm-project-15.0.7/lldb/source/Plugins/Instruction/MIPS64/ |
| H A D | EmulateInstructionMIPS64.cpp | 1985 uint32_t cc, fcsr; in Emulate_FP_branch() local
2003 fcsr = in Emulate_FP_branch()
2009 fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01); in Emulate_FP_branch()
2013 if ((fcsr & (1 << cc)) == 0) in Emulate_FP_branch()
2019 if ((fcsr & (1 << cc)) != 0) in Emulate_FP_branch()
2112 uint32_t cc, fcsr; in Emulate_3D_branch() local
2129 fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01); in Emulate_3D_branch()
2133 if (((fcsr >> cc) & 3) != 3) in Emulate_3D_branch()
2139 if (((fcsr >> cc) & 3) != 0) in Emulate_3D_branch()
2145 if (((fcsr >> cc) & 0xf) != 0xf) in Emulate_3D_branch()
[all …]
|
| /llvm-project-15.0.7/lldb/source/Plugins/Instruction/MIPS/ |
| H A D | EmulateInstructionMIPS.cpp | 2672 uint32_t cc, fcsr; in Emulate_FP_branch() local
2688 fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01); in Emulate_FP_branch()
2692 if ((fcsr & (1 << cc)) == 0) in Emulate_FP_branch()
2698 if ((fcsr & (1 << cc)) != 0) in Emulate_FP_branch()
2790 uint32_t cc, fcsr; in Emulate_3D_branch() local
2801 fcsr = (uint32_t)ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_fcsr_mips, 0, in Emulate_3D_branch()
2807 fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01); in Emulate_3D_branch()
2811 if (((fcsr >> cc) & 3) != 3) in Emulate_3D_branch()
2817 if (((fcsr >> cc) & 3) != 0) in Emulate_3D_branch()
2823 if (((fcsr >> cc) & 0xf) != 0xf) in Emulate_3D_branch()
[all …]
|
| /llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/ |
| H A D | RegisterContext_mips.h | 319 uint32_t fcsr; member
361 uint32_t fcsr; /* FPU control status register */ member
|
| H A D | RegisterContextFreeBSD_mips64.cpp | 141 uint64_t fcsr; member
|
| H A D | RegisterInfos_mips.h | 211 DEFINE_FPR_INFO(fcsr, nullptr, dwarf_fcsr_mips, dwarf_fcsr_mips,
285 DEFINE_MSA_INFO(fcsr, nullptr, dwarf_fcsr_mips, dwarf_fcsr_mips,
|
| H A D | RegisterInfos_mips64.h | 203 DEFINE_FPR_INFO(fcsr, nullptr, dwarf_fcsr_mips64, dwarf_fcsr_mips64,
|
| /llvm-project-15.0.7/compiler-rt/test/asan/TestCases/Linux/ |
| H A D | ptrace.cpp | 75 #define PRINT_REG_FP(__fpregs) printf("%lx\n", (unsigned long)(__fpregs.fcsr))
|
| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchRegisterInfo.td | 158 def FCSR#I : LoongArchReg<I, "fcsr"#I>;
|
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVSystemOperands.td | 96 def SysRegFCSR : SysReg<"fcsr", 0x003>;
|