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/llvm-project-15.0.7/llvm/test/tools/llvm-reduce/
H A Dreduce-operands-fp.ll15 ; CHECK-INTERESTINGNESS: = fadd float %
16 ; CHECK-INTERESTINGNESS: = fadd float
17 ; CHECK-INTERESTINGNESS: = fadd float
18 ; CHECK-INTERESTINGNESS: = fadd float
19 ; CHECK-INTERESTINGNESS: = fadd float
20 ; CHECK-INTERESTINGNESS: = fadd float
79 %fadd0 = fadd float %arg0, %arg1
80 %fadd1 = fadd float %arg0, %arg1
81 %fadd2 = fadd float %arg0, 0.0
82 %fadd3 = fadd float %arg0, 1.0
[all …]
/llvm-project-15.0.7/polly/test/ScopDetect/
H A Dprofitability-large-basic-blocks.ll31 %val0 = fadd float %tmp7, 1.0
32 %val1 = fadd float %val0, 1.0
33 %val2 = fadd float %val1, 1.0
34 %val3 = fadd float %val2, 1.0
35 %val4 = fadd float %val3, 1.0
36 %val5 = fadd float %val4, 1.0
37 %val6 = fadd float %val5, 1.0
38 %val7 = fadd float %val6, 1.0
39 %val8 = fadd float %val7, 1.0
40 %val9 = fadd float %val8, 1.0
[all …]
/llvm-project-15.0.7/llvm/test/Bitcode/
H A DbinaryFloatInstructions.3.2.ll10 ; CHECK: %res1 = fadd float %x1, %x1
11 %res1 = fadd float %x1, %x1
14 %res2 = fadd double %x2, %x2
17 %res3 = fadd half %x3, %x3
20 %res4 = fadd fp128 %x4, %x4
23 %res5 = fadd x86_fp80 %x5, %x5
26 %res6 = fadd ppc_fp128 %x6, %x6
34 %res1 = fadd <2 x float> %x1, %x1
37 %res2 = fadd <3 x float> %x2, %x2
40 %res3 = fadd <4 x float> %x3, %x3
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/Reassociate/
H A Dfast-ArrayOutOfBounds.ll24 %tmp.2 = fadd float %a4, %a3
25 %tmp.4 = fadd float %tmp.2, %a2
26 %tmp.6 = fadd float %tmp.4, %a1
27 %tmp.8 = fadd float %tmp.6, %a0
28 %tmp.11 = fadd float %a3, %a2
29 %tmp.13 = fadd float %tmp.11, %a1
30 %tmp.15 = fadd float %tmp.13, %a0
31 %tmp.18 = fadd float %a2, %a1
32 %tmp.20 = fadd float %tmp.18, %a0
33 %tmp.23 = fadd float %a1, %a0
[all …]
H A Dfast-SubReassociate.ll12 %W = fadd float 5.0, %B
13 %X = fadd float -7.0, %A
15 %Z = fadd float %Y, 12.0
71 %M = fadd float %A, 1.200000e+01
72 %N = fadd float %M, %B
73 %O = fadd float %N, %C
75 %Q = fadd float %P, 1.200000e+01
89 %N = fadd fast float %M, %B
90 %O = fadd fast float %N, %C
108 %N = fadd reassoc float %M, %B
[all …]
H A Dfast-MissedTree.ll5 ; CHECK-NEXT: [[Z:%.*]] = fadd fast float %A, %B
8 %W = fadd fast float %B, -5.0
9 %Y = fadd fast float %A, 5.0
10 %Z = fadd fast float %W, %Y
18 ; CHECK-NEXT: [[Z:%.*]] = fadd reassoc nsz float %A, %B
21 %W = fadd reassoc nsz float %B, -5.0
22 %Y = fadd reassoc nsz float %A, 5.0
23 %Z = fadd reassoc nsz float %W, %Y
35 %W = fadd reassoc float %B, -5.0
36 %Y = fadd reassoc float %A, 5.0
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/RISCV/
H A Dreduce-fadd.ll136 declare half @llvm.vector.reduce.fadd.v1f16(half, <1 x half>)
137 declare half @llvm.vector.reduce.fadd.v2f16(half, <2 x half>)
138 declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>)
139 declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>)
140 declare half @llvm.vector.reduce.fadd.v16f16(half, <16 x half>)
141 declare half @llvm.vector.reduce.fadd.v32f16(half, <32 x half>)
142 declare half @llvm.vector.reduce.fadd.v64f16(half, <64 x half>)
144 declare float @llvm.vector.reduce.fadd.v1f32(float, <1 x float>)
145 declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>)
146 declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmachine-combiner.ll17 %t0 = fadd float %x0, %x1
18 %t1 = fadd float %t0, %x2
19 %t2 = fadd float %t1, %x3
29 %t0 = fadd float %x0, %x1
30 %t1 = fadd float %x2, %t0
31 %t2 = fadd float %t1, %x3
41 %t0 = fadd float %x0, %x1
42 %t1 = fadd float %t0, %x2
43 %t2 = fadd float %x3, %t1
53 %t0 = fadd float %x0, %x1
[all …]
H A Dvecreduce-fadd-legalization-strict.ll21 ; CHECK-NEXT: fadd s0, s1, s0
40 ; CHECK-NEXT: fadd s0, s1, s0
59 ; CHECK-NEXT: fadd d0, d1, d0
95 ; CHECK-NEXT: fadd s1, s1, s0
98 ; CHECK-NEXT: fadd s1, s1, s2
99 ; CHECK-NEXT: fadd s0, s1, s0
110 ; CHECK-NEXT: fadd s0, s0, s1
119 ; CHECK-NEXT: fadd s0, s5, s0
120 ; CHECK-NEXT: fadd s0, s0, s1
121 ; CHECK-NEXT: fadd s0, s0, s2
[all …]
H A Dfadd-combines.ll7 ; CHECK-NEXT: fadd d1, d1, d1
11 %add1 = fadd double %a, %mul
20 ; CHECK-NEXT: fadd d1, d1, d1
31 ; CHECK-NEXT: fadd d2, d2, d2
44 ; CHECK-NEXT: fadd d2, d2, d2
50 %add2 = fadd double %mul, %mul1
109 ; Don't fold (fadd A, (fmul B, -2.0)) -> (fsub A, (fadd B, B)) if the fmul has
127 %add1 = fadd double %a, %mul
143 %a1 = fadd float %x, 42.0
145 %a3 = fadd float %a1, %a2
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A DVSX-DForm-Scalars.ll16 %add = fadd double %a, %b
17 %add1 = fadd double %add, %c
18 %add2 = fadd double %add1, %d
19 %add3 = fadd double %add2, %e
20 %add4 = fadd double %add3, %f
21 %add5 = fadd double %add4, %g
22 %add6 = fadd double %add5, %h
23 %add7 = fadd double %add6, %i
24 %add8 = fadd double %add7, %j
50 %add = fadd float %a, %b
[all …]
H A Dmachine-combiner.ll17 %t0 = fadd reassoc nsz float %x0, %x1
18 %t1 = fadd reassoc nsz float %t0, %x2
19 %t2 = fadd reassoc nsz float %t1, %x3
31 %t0 = fadd reassoc nsz float %x0, %x1
32 %t1 = fadd reassoc nsz float %x2, %t0
33 %t2 = fadd reassoc nsz float %t1, %x3
45 %t0 = fadd reassoc nsz float %x0, %x1
150 %t1 = fadd float %x2, %t0
151 %t2 = fadd float %x3, %t1
164 %t1 = fadd double %x2, %t0
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A Dfpmath.ll5 ; CHECK: %add1 = fadd double %x, %y
7 ; CHECK: %foo = fadd double %add1, %add1
8 %add1 = fadd double %x, %y, !fpmath !0
9 %add2 = fadd double %x, %y
10 %foo = fadd double %add1, %add2
17 ; CHECK: %foo = fadd double %add1, %add1
18 %add1 = fadd double %x, %y, !fpmath !0
20 %foo = fadd double %add1, %add2
30 %foo = fadd double %add1, %add2
40 %foo = fadd double %add1, %add2
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/GVN/
H A Dfpmath.ll5 ; CHECK: %add1 = fadd double %x, %y
7 ; CHECK: %foo = fadd double %add1, %add1
8 %add1 = fadd double %x, %y, !fpmath !0
9 %add2 = fadd double %x, %y
10 %foo = fadd double %add1, %add2
17 ; CHECK: %foo = fadd double %add1, %add1
18 %add1 = fadd double %x, %y, !fpmath !0
20 %foo = fadd double %add1, %add2
30 %foo = fadd double %add1, %add2
40 %foo = fadd double %add1, %add2
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/
H A Dreduce-fadd.ll77 declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>)
78 declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>)
79 declare half @llvm.vector.reduce.fadd.v11f16(half, <11 x half>)
80 declare half @llvm.vector.reduce.fadd.v13f16(half, <13 x half>)
82 declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>)
83 declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>)
84 declare float @llvm.vector.reduce.fadd.v13f32(float, <13 x float>)
85 declare float @llvm.vector.reduce.fadd.v5f32(float, <5 x float>)
87 declare double @llvm.vector.reduce.fadd.v2f64(double, <2 x double>)
88 declare double @llvm.vector.reduce.fadd.v4f64(double, <4 x double>)
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/SVE/
H A Dfadd.s18 fadd z0.h, p0/m, z0.h, #0.5 label
24 fadd z0.s, p0/m, z0.s, #0.5 label
30 fadd z0.d, p0/m, z0.d, #0.5 label
42 fadd z31.h, p7/m, z31.h, #1.0 label
48 fadd z31.s, p7/m, z31.s, #1.0 label
60 fadd z0.h, p7/m, z0.h, z31.h label
66 fadd z0.s, p7/m, z0.s, z31.s label
72 fadd z0.d, p7/m, z0.d, z31.d label
78 fadd z0.h, z1.h, z31.h label
84 fadd z0.s, z1.s, z31.s label
[all …]
H A Dfadd-diagnostics.s6 fadd z0.h, p0/m, z0.h, #0.0 label
11 fadd z0.h, p0/m, z0.h, #0.4999999999999999999999999 label
16 fadd z0.h, p0/m, z0.h, #0.5000000000000000000000001 label
35 fadd z0.h, p7/m, z1.h, z31.h label
44 fadd z0.b, p7/m, z0.b, z31.b label
49 fadd z0.h, p7/m, z0.h, z31.s label
54 fadd z0.b, z1.b, z2.b label
59 fadd z0.h, z1.s, z2.s label
67 fadd z0.h, p8/m, z0.h, z31.h label
77 fadd z0.d, z1.d, z31.d label
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AMDGPU/
H A Dfadd.ll51 %f32 = fadd float undef, undef
52 %v2f32 = fadd <2 x float> undef, undef
53 %v3f32 = fadd <3 x float> undef, undef
54 %v4f32 = fadd <4 x float> undef, undef
55 %v5f32 = fadd <5 x float> undef, undef
56 %v8f32 = fadd <8 x float> undef, undef
57 %v9f32 = fadd <9 x float> undef, undef
102 %f64 = fadd double undef, undef
151 %f16 = fadd half undef, undef
152 %v2f16 = fadd <2 x half> undef, undef
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dnsa-reassign.ll9 %s1.1 = fadd float %s1, 1.0
10 %t1.1 = fadd float %t1, 1.0
11 %r1.1 = fadd float %r1, 1.0
12 %s2.1 = fadd float %s2, 1.0
13 %t2.1 = fadd float %t2, 1.0
14 %r2.1 = fadd float %r2, 1.0
15 %lod.1 = fadd float %lod, 1.0
29 %s1.1 = fadd float %s1, 1.0
30 %t1.1 = fadd float %t1, 1.0
31 %r1.1 = fadd float %r1, 1.0
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/X86/
H A Dreduce-fadd.ll290 declare double @llvm.vector.reduce.fadd.v1f64(double, <1 x double>)
291 declare double @llvm.vector.reduce.fadd.v2f64(double, <2 x double>)
292 declare double @llvm.vector.reduce.fadd.v4f64(double, <4 x double>)
293 declare double @llvm.vector.reduce.fadd.v8f64(double, <8 x double>)
294 declare double @llvm.vector.reduce.fadd.v16f64(double, <16 x double>)
296 declare float @llvm.vector.reduce.fadd.v1f32(float, <1 x float>)
297 declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>)
298 declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>)
299 declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>)
300 declare float @llvm.vector.reduce.fadd.v16f32(float, <16 x float>)
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/Inline/AMDGPU/
H A Damdgpu-inline-alloca-argument.ll10 %add0 = fadd float %div, 1.0
11 %add1 = fadd float %add0, 1.0
12 %add2 = fadd float %add1, 1.0
13 %add3 = fadd float %add2, 1.0
14 %add4 = fadd float %add3, 1.0
15 %add5 = fadd float %add4, 1.0
16 %add6 = fadd float %add5, 1.0
17 %add7 = fadd float %add6, 1.0
18 %add8 = fadd float %add7, 1.0
19 %add9 = fadd float %add8, 1.0
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dhorizontal-list.ll48 %add = fadd fast float %mul4, %conv
184 %5 = fadd fast float %mul.1, %mul
188 %8 = fadd fast float %mul.2, %5
192 %11 = fadd fast float %mul.3, %8
234 %5 = fadd fast float %mul.1, %mul
238 %8 = fadd fast float %mul.2, %5
242 %11 = fadd fast float %mul.3, %8
348 %add.1 = fadd fast float %1, %0
515 %add = fadd fast float %0, %conv
671 %add.1 = fadd fast float %1, %0
[all …]
H A Dpr19657.ll35 %2 = fadd double %1, %1
36 %3 = fadd double %2, %1
40 %6 = fadd double %5, %5
41 %7 = fadd double %6, %5
45 %10 = fadd double %9, %9
46 %11 = fadd double %10, %9
74 %2 = fadd double %1, %1
75 %3 = fadd double %2, %1
79 %6 = fadd double %5, %5
80 %7 = fadd double %6, %5
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dframe-02.ll56 %add0 = fadd float %l0, %l0
57 %add1 = fadd float %l1, %add0
58 %add2 = fadd float %l2, %add1
59 %add3 = fadd float %l3, %add2
60 %add4 = fadd float %l4, %add3
61 %add5 = fadd float %l5, %add4
62 %add6 = fadd float %l6, %add5
63 %add7 = fadd float %l7, %add6
64 %add8 = fadd float %l8, %add7
65 %add9 = fadd float %l9, %add8
[all …]
H A Dframe-03.ll58 %add0 = fadd double %l0, %l0
59 %add1 = fadd double %l1, %add0
60 %add2 = fadd double %l2, %add1
61 %add3 = fadd double %l3, %add2
62 %add4 = fadd double %l4, %add3
63 %add5 = fadd double %l5, %add4
64 %add6 = fadd double %l6, %add5
65 %add7 = fadd double %l7, %add6
66 %add8 = fadd double %l8, %add7
67 %add9 = fadd double %l9, %add8
[all …]

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