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/llvm-project-15.0.7/llvm/test/MC/Sparc/
H A Dsparc-fp-instructions.s6 fitos %f0, %f4
7 fitod %f0, %f4
8 fitoq %f0, %f4
13 fstoi %f0, %f4
14 fdtoi %f0, %f4
15 fqtoi %f0, %f4
19 fstod %f0, %f4
20 fstoq %f0, %f4
24 fdtos %f0, %f4
25 fdtoq %f0, %f4
[all …]
H A Dsparcv8-instructions.s3 ! CHECK: fcmps %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x24]
4 ! CHECK: fcmpd %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x44]
5 ! CHECK: fcmpq %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x64]
6 fcmps %f0, %f4
7 fcmpd %f0, %f4
8 fcmpq %f0, %f4
10 ! CHECK: fcmpes %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xa4]
11 ! CHECK: fcmped %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xc4]
13 fcmpes %f0, %f4
14 fcmped %f0, %f4
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A Dvector.ll29 define void @test_f4(%f4* %P, %f4* %Q, %f4* %S) {
30 %p = load %f4, %f4* %P ; <%f4> [#uses=1]
31 %q = load %f4, %f4* %Q ; <%f4> [#uses=1]
33 store %f4 %R, %f4* %S
65 %p = load %f4, %f4* %P ; <%f4> [#uses=1]
67 store %f4 %R, %f4* %S
72 %p = load %f4, %f4* %P ; <%f4> [#uses=1]
74 store %f4 %R, %f4* %S
79 %p = load %f4, %f4* %P ; <%f4> [#uses=1]
116 %tmp = load %f4, %f4* %b ; <%f4> [#uses=1]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dvector.ll30 define void @test_f4(%f4* %P, %f4* %Q, %f4* %S) {
31 %p = load %f4, %f4* %P ; <%f4> [#uses=1]
32 %q = load %f4, %f4* %Q ; <%f4> [#uses=1]
34 store %f4 %R, %f4* %S
73 %p = load %f4, %f4* %P ; <%f4> [#uses=1]
76 store %f4 %R, %f4* %S
83 store %f4 %R, %f4* %S
90 store %f4 %R, %f4* %S
97 store %f4 %R, %f4* %S
103 store %f4 %R, %f4* %S
[all …]
H A Dscalar_cmp.ll43 ; NO-FAST-P8-NEXT: fmr f1, f4
51 ; NO-FAST-P9-NEXT: fmr f3, f4
84 ; NO-FAST-P8-NEXT: fmr f1, f4
92 ; NO-FAST-P9-NEXT: fmr f3, f4
204 ; NO-FAST-P8-NEXT: fmr f1, f4
213 ; NO-FAST-P9-NEXT: fmr f3, f4
247 ; NO-FAST-P8-NEXT: fmr f1, f4
256 ; NO-FAST-P9-NEXT: fmr f3, f4
364 ; NO-FAST-P8-NEXT: fmr f1, f4
373 ; NO-FAST-P9-NEXT: fmr f3, f4
[all …]
H A Dscalar-equal.ll24 ; FAST-P8-NEXT: fsel f0, f0, f3, f4
25 ; FAST-P8-NEXT: fsel f1, f1, f0, f4
31 ; FAST-P9-NEXT: fsel f1, f0, f3, f4
33 ; FAST-P9-NEXT: fsel f1, f0, f1, f4
41 ; NO-FAST-P9-NEXT: fmr f3, f4
52 ; NO-FAST-P8-NEXT: fmr f1, f4
65 ; FAST-P8-NEXT: fsel f0, f0, f3, f4
66 ; FAST-P8-NEXT: fsel f1, f1, f0, f4
72 ; FAST-P9-NEXT: fsel f1, f0, f3, f4
74 ; FAST-P9-NEXT: fsel f1, f0, f1, f4
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Sparc/
H A Dsparc-fp.txt4 # CHECK: fitos %f0, %f4
7 # CHECK: fitod %f0, %f4
10 # CHECK: fitoq %f0, %f4
13 # CHECK: fstoi %f0, %f4
16 # CHECK: fdtoi %f0, %f4
19 # CHECK: fqtoi %f0, %f4
22 # CHECK: fstod %f0, %f4
24 # CHECK: fstoq %f0, %f4
27 # CHECK: fdtos %f0, %f4
30 # CHECK: fdtoq %f0, %f4
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips32r6/
H A Dvalid.s179 add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30]
180 add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30]
182 sub.s $f3, $f4, $f5 # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70]
183 sub.d $f2, $f4, $f6 # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70]
185 mul.s $f3, $f4, $f5 # CHECK: mul.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xb0]
186 mul.d $f2, $f4, $f6 # CHECK: mul.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xb0]
188 div.s $f3, $f4, $f5 # CHECK: div.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xf0]
189 div.d $f2, $f4, $f6 # CHECK: div.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xf0]
196 mov.d $f4, $f6 # CHECK: mov.d $f4, $f6 # encoding: [0x54,0x86,0x20,0x7b]
260 floor.l.d $f2, $f4 # CHECK: floor.l.d $f2, $f4 # encoding: [0x54,0x44,0x43,0x3b]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvector.ll8 %f4 = type <4 x float>
32 %p = load %f4, ptr %P ; <%f4> [#uses=1]
33 %q = load %f4, ptr %Q ; <%f4> [#uses=1]
34 %R = fadd %f4 %p, %q ; <%f4> [#uses=1]
66 %p = load %f4, ptr %P ; <%f4> [#uses=1]
73 %p = load %f4, ptr %P ; <%f4> [#uses=1]
80 %p = load %f4, ptr %P ; <%f4> [#uses=1]
81 %R = fadd %f4 %p, undef ; <%f4> [#uses=1]
117 %tmp = load %f4, ptr %b ; <%f4> [#uses=1]
140 %q = load %f4, ptr %Q ; <%f4> [#uses=1]
[all …]
H A Dvec_align.ll7 %f4 = type <4 x float>
16 %tmp = insertelement %f4 undef, float %W, i32 0
17 %tmp2 = insertelement %f4 %tmp, float %X, i32 1
18 %tmp4 = insertelement %f4 %tmp2, float %Y, i32 2
19 %tmp6 = insertelement %f4 %tmp4, float %Z, i32 3
20 ret %f4 %tmp6
23 define %f4 @test2() nounwind {
38 %tmp = insertelement %f4 undef, float %W, i32 0
39 %tmp2 = insertelement %f4 %tmp, float %X, i32 1
40 %tmp4 = insertelement %f4 %tmp2, float %Y, i32 2
[all …]
/llvm-project-15.0.7/clang/test/SemaTemplate/
H A Dtemplate-id-expr.cpp61 static int f4(int);
63 static void f4(U);
78 x = Y0::f4(0); in f()
79 x = Y0::f4<int>(0); // expected-error {{assigning to 'int' from incompatible type 'void'}} in f()
82 x = this->f4(0); in f()
105 static int f4(int);
107 static void f4(U);
122 x = Y1::f4(0); in f()
126 x = this->f4(0); in f()
151 x = Y1::f4(0); in f()
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r6/
H A Dvalid-mips32r6-el.txt119 0x1d 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4
120 0x1d 0x10 0x24 0x46 # CHECK: max.d $f0, $f2, $f4
121 0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4
122 0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4
123 0x1f 0x10 0x04 0x46 # CHECK: maxa.s $f0, $f2, $f4
124 0x1f 0x10 0x24 0x46 # CHECK: maxa.d $f0, $f2, $f4
134 0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4
135 0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4
137 0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
138 0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4
[all …]
H A Dvalid-mips32r6.txt89 0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4
90 0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4
94 0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4
95 0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4
96 0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4
97 0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4
100 0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4
101 0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4
105 0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4
106 0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/micromips32r6/
H A Dvalid.txt140 0x54 0x86 0x20 0x7b # CHECK: mov.d $f4, $f6
142 0x54 0x86 0x2b 0x7b # CHECK: neg.d $f4, $f6
183 0x54 0x64 0x01 0x3b # CHECK: cvt.l.s $f3, $f4
184 0x54 0x64 0x41 0x3b # CHECK: cvt.l.d $f3, $f4
185 0x54 0x64 0x09 0x3b # CHECK: cvt.w.s $f3, $f4
186 0x54 0x64 0x49 0x3b # CHECK: cvt.w.d $f3, $f4
194 0x54 0x44 0x23 0x7b # CHECK: abs.d $f2, $f4
208 0x54 0x44 0x4a 0x3b # CHECK: sqrt.d $f2, $f4
265 0x54 0x82 0x00 0x20 # CHECK: rint.s $f2, $f4
266 0x54 0x82 0x02 0x20 # CHECK: rint.d $f2, $f4
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r6/
H A Dvalid-mips64r6-el.txt61 0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4
62 0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4
143 0x1d 0x10 0x24 0x46 # CHECK: max.d $f0, $f2, $f4
144 0x1d 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4
145 0x1f 0x10 0x24 0x46 # CHECK: maxa.d $f0, $f2, $f4
146 0x1f 0x10 0x04 0x46 # CHECK: maxa.s $f0, $f2, $f4
148 0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4
149 0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4
167 0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4
168 0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4
[all …]
H A Dvalid-mips64r6.txt108 0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4
109 0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4
113 0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4
114 0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4
115 0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4
116 0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4
119 0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4
120 0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4
124 0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4
125 0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmicromips-fpu-instructions.s319 add.s $f4, $f6, $f8
320 add.d $f4, $f6, $f8
321 div.s $f4, $f6, $f8
322 div.d $f4, $f6, $f8
323 mul.s $f4, $f6, $f8
324 mul.d $f4, $f6, $f8
325 sub.s $f4, $f6, $f8
361 movz.s $f4, $f6, $7
362 movz.d $f4, $f6, $7
363 movn.s $f4, $f6, $7
[all …]
/llvm-project-15.0.7/clang/test/SemaCUDA/
H A Dimplicit-device-lambda.cu18 auto f4 = [&] __host__ __device__ {}; in device_fn() local
19 f4(); in device_fn()
60 auto f4 = [&] __host__ __device__ {}; in kernel_fn() local
61 f4(); in kernel_fn()
77 auto f4 = [&] __host__ __device__ {}; in host_fn() local
78 f4(); in host_fn()
97 auto f4 = [&] __host__ __device__ {}; in hd_fn() local
98 f4(); in hd_fn()
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dasm-17.ll31 ; CHECK: lzer %f4
32 ; CHECK: blah %f4
33 ; CHECK: ler %f0, %f4
40 define double @f4() {
41 ; CHECK-LABEL: f4:
42 ; CHECK: lzdr %f4
43 ; CHECK: blah %f4
44 ; CHECK: ldr %f0, %f4
53 ; CHECK: lzxr %f4
54 ; CHECK: blah %f4
[all …]
H A Dshorten-fused-fp-ops.mir11 # CHECK: madbr %f0, %f4, %f2
12 # CHECK-NEXT: wfmadb %f0, %f4, %v16, %f0
13 # CHECK-NEXT: wfmadb %f0, %f4, %f0, %f2
14 # CHECK-NEXT: maebr %f0, %f4, %f2
15 # CHECK-NEXT: wfmasb %f0, %f4, %v16, %f0
16 # CHECK-NEXT: wfmasb %f0, %f4, %f0, %f2
17 # CHECK-NEXT: msdbr %f0, %f4, %f2
18 # CHECK-NEXT: wfmsdb %f0, %f4, %v16, %f0
19 # CHECK-NEXT: wfmsdb %f0, %f4, %f0, %f2
20 # CHECK-NEXT: msebr %f0, %f4, %f2
[all …]
/llvm-project-15.0.7/clang/test/SemaOpenCL/
H A Doperators.cl44 float4 f4 = (float4)(0, 0, 0, 0);
45 int4 f4laf = f4 && 0.0f;
49 int4 f4lof = f4 || 0.0f;
53 float4 f4baf = f4 & 0.0f; // expected-error {{invalid operands}}
56 float bnf4 = ~f4; // expected-error {{invalid argument type}}
57 int4 lnf4 = !f4;
97 double4 f4 = (double4)(0, 0, 0, 0);
98 long4 f4laf = f4 && 0.0;
102 long4 f4lof = f4 || 0.0;
109 double bnf4 = ~f4; // expected-error {{invalid argument type}}
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips/
H A Dvalid-fp64.s9 add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x30]
19 cvt.l.s $f4, $f2 # CHECK: cvt.l.s $f4, $f2 # encoding: [0x54,0x82,0x01,0x3b]
21 cvt.l.d $f4, $f2 # CHECK: cvt.l.d $f4, $f2 # encoding: [0x54,0x82,0x41,0x3b]
23 div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xf0]
31 mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xb0]
39 sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x70]
/llvm-project-15.0.7/flang/test/Semantics/
H A Dresolve59.f9039 function f4() function
40 procedure(rf), pointer :: f4 local
41 f4 => rf
43 x = acos(f4())
45 x = acos(f4)
103 function f4() result(r) function
108 x = acos(f4()) ! recursive call
110 x = acos(f4)
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/micromips32r3/
H A Dvalid-fp64.txt10 0x54 0x82 0x01 0x30 # CHECK: add.d $f0, $f2, $f4
11 0x54 0x82 0x01 0x70 # CHECK: sub.d $f0, $f2, $f4
12 0x54 0x82 0x01 0xb0 # CHECK: mul.d $f0, $f2, $f4
13 0x54 0x82 0x01 0xf0 # CHECK: div.d $f0, $f2, $f4
20 0x54 0x82 0x01 0x3b # CHECK: cvt.l.s $f4, $f2
21 0x54 0x82 0x41 0x3b # CHECK: cvt.l.d $f4, $f2
22 0x54 0x85 0x21 0x48 # CHECK: luxc1 $f4, $4($5)
23 0x54 0x85 0x21 0x88 # CHECK: suxc1 $f4, $4($5)
H A Dvalid-fp64-el.txt10 0x82 0x54 0x30 0x01 # CHECK: add.d $f0, $f2, $f4
11 0x82 0x54 0x70 0x01 # CHECK: sub.d $f0, $f2, $f4
12 0x82 0x54 0xb0 0x01 # CHECK: mul.d $f0, $f2, $f4
13 0x82 0x54 0xf0 0x01 # CHECK: div.d $f0, $f2, $f4
20 0x82 0x54 0x3b 0x01 # CHECK: cvt.l.s $f4, $f2
21 0x82 0x54 0x3b 0x41 # CHECK: cvt.l.d $f4, $f2
22 0x85 0x54 0x48 0x21 # CHECK: luxc1 $f4, $4($5)
23 0x85 0x54 0x88 0x21 # CHECK: suxc1 $f4, $4($5)

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