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/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r2/
H A Dvalid-xfail-mips64r2.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
37 0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
39 0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
48 0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
54 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
62 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
64 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r3/
H A Dvalid-xfail-mips64r3.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
37 0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
39 0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
48 0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
54 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
62 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
64 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r5/
H A Dvalid-xfail-mips64r5.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
37 0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
39 0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
48 0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
54 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
62 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
64 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r3/
H A Dvalid-xfail-mips32r3.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
38 0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
40 0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
53 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
54 0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
61 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
68 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
[all …]
H A Dvalid-fp64-el.txt19 0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
22 0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2
23 0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r5/
H A Dvalid-xfail-mips32r5.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
38 0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
40 0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
53 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
54 0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
61 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
68 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
[all …]
H A Dvalid-fp64-el.txt19 0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
22 0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2
23 0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r2/
H A Dvalid-xfail-mips32r2.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
38 0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
40 0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
53 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
54 0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
61 0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
68 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64/
H A Dvalid-mips64-xfail.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
33 0x4d 0x9e 0x93 0x1e # CHECK: alnv.ps $f12, $f18, $f30, $8
39 0x46 0xde 0xa8 0x3b # CHECK: c.ngl.ps $f21, $f30
41 0x46 0xc6 0xf5 0x3f # CHECK: c.ngt.ps $fcc5, $f30, $f6
51 0x46 0xc0 0x0f 0xa8 # CHECK: cvt.s.pl $f30, $f1
69 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
72 0x46 0xde 0x4e 0x6c # CHECK: pll.ps $f25, $f9, $f30
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmips-reginfo-fp32.s33 # abs.d - Reads from $f30 and $f31 and writes to $f30 and $f31.
34 abs.d $f30,$f30
H A Dmips-reginfo-fp64.s55 # abs.d - Reads from $f30 and writes to $f30.
56 abs.d $f30,$f30
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r3/
H A Dvalid.s47 …c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0…
60 …c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0…
98 … cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
108 … cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8]
249 movt.s $f30,$f2,$fcc1
265 mul.s $f30,$f10,$f2
286 … pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
288 …plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
291 … pul.ps $f9,$f30,$f26 # CHECK: pul.ps $f9, $f30, $f26 # encoding: [0x46,0xda,0xf2,0x6e]
302 … recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r2/
H A Dvalid.s48 …c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0…
61 …c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0…
99 … cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
109 … cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8]
256 movt.s $f30,$f2,$fcc1
272 mul.s $f30,$f10,$f2
293 … pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
295 …plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
298 … pul.ps $f9,$f30,$f26 # CHECK: pul.ps $f9, $f30, $f26 # encoding: [0x46,0xda,0xf2,0x6e]
311 … recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r5/
H A Dvalid.s47 …c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0…
60 …c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0…
98 … cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
108 … cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8]
251 movt.s $f30,$f2,$fcc1
267 mul.s $f30,$f10,$f2
288 … pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
290 …plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
293 … pul.ps $f9,$f30,$f26 # CHECK: pul.ps $f9, $f30, $f26 # encoding: [0x46,0xda,0xf2,0x6e]
304 … recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64/
H A Dvalid.s47 …c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0…
60 …c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0…
64 …c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0…
66 …c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0…
69 …c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0…
98 … cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
227 movt.s $f30,$f2,$fcc1
242 mul.s $f30,$f10,$f2
255 nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
265 … recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips4/
H A Dvalid.s47 …c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0…
60 …c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0…
64 …c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0…
66 …c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0…
69 …c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0…
96 … cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
214 movt.s $f30,$f2,$fcc1
225 mul.s $f30,$f10,$f2
238 nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
248 … recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
[all …]
H A Dinvalid-mips5.s12 …cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
17 …pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/llvm-project-15.0.7/llvm/test/MC/Mips/mips5/
H A Dvalid.s47 …c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0…
60 …c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0…
64 …c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0…
66 …c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0…
69 …c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0…
96 … cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
215 movt.s $f30,$f2,$fcc1
226 mul.s $f30,$f10,$f2
239 nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
249 … recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r5/
H A Dvalid.s50 …c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0…
63 …c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0…
67 …c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0…
69 …c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0…
72 …c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0…
74 …c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0…
172 movt.s $f30,$f2,$fcc1
190 mul.s $f30,$f10,$f2
204 nmsub.d $f30,$f8,$f16,$f30
222 … recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s50 …c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0…
63 …c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0…
67 …c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0…
69 …c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0…
72 …c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0…
74 …c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0…
171 movt.s $f30,$f2,$fcc1
189 mul.s $f30,$f10,$f2
203 nmsub.d $f30,$f8,$f16,$f30
221 … recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r3/
H A Dvalid.s50 …c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0…
63 …c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0…
67 …c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0…
69 …c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0…
72 …c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0…
74 …c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0…
171 movt.s $f30,$f2,$fcc1
189 mul.s $f30,$f10,$f2
203 nmsub.d $f30,$f8,$f16,$f30
221 … recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32/
H A Dvalid.s50 …c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0…
63 …c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0…
67 …c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0…
69 …c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0…
72 …c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0…
74 …c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0…
78 …c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0…
155 movt.s $f30,$f2,$fcc1
169 mul.s $f30,$f10,$f2
311 … trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
/llvm-project-15.0.7/lldb/test/Shell/ObjectFile/Breakpad/Inputs/
H A Didentification-macosx.syms3 PUBLIC f30 0 start
4 STACK CFI INIT f30 6 .cfa: $rsp 8 + .ra: .cfa -8 + ^
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32/
H A Dvalid-xfail-mips32.txt6 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
24 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
30 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Derror-location.s27 .byte f30(PLT)
30 .hword f30(PLT)
33 .word f30(PLT)

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