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/llvm-project-15.0.7/llvm/test/MC/Sparc/
H A Dsparc-fp-instructions.s141 ! CHECK: ld [%l0], %f29 ! encoding: [0xfb,0x04,0x00,0x00]
143 ld [%l0], %f29
146 ! CHECK: st %f29, [%l0] ! encoding: [0xfb,0x24,0x00,0x00]
148 st %f29, [%l0]
H A Dsparcv9-instructions.s57 ! V8-NEXT: lda [%l0] 0xf0, %f29
58 ! V9: lda [%l0] 240, %f29 ! encoding: [0xfb,0x84,0x1e,0x00]
59 lda [%l0] 0xf0, %f29
76 ! V8-NEXT: sta %f29, [%l0] 0xf0
77 ! V9: sta %f29, [%l0] 240 ! encoding: [0xfb,0xa4,0x1e,0x00]
78 sta %f29, [%l0] 0xf0
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Dcallee-saved-float.ll28 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
70 ; O32-INV-NOT: sdc1 $f29,
89 ; N32-INV-NOT: sdc1 $f29,
102 ; N64-DAG: sdc1 [[F29:\$f29]], [[OFF29:[0-9]+]]($sp)
H A Dcallee-saved-fpxx.ll13 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
42 ; O32-FPXX-INV-NOT: sdc1 $f29,
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dno-odd-spreg-msa.ll26 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
60 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
90 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
118 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
H A Dno-odd-spreg.ll32 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
56 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips1.s11 …c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dsymbol-variants.s95 .word f29(tlsldm)
97 @CHECK: 74 R_ARM_TLS_LDM32 f29
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-csr-alloc.ll20 …= [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25…
27 …= [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25…
H A Dvsx-spill.ll21 …8},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() n…
54 …8},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() n…
85 …8},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0…
/llvm-project-15.0.7/llvm/test/MC/Mips/mips4/
H A Dinvalid-mips5-wrong-error.s23 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
33 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips1.s14 …c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
H A Dinvalid-mips5-wrong-error.s26 … c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
36 … msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/MC/Mips/mips3/
H A Dinvalid-mips5-wrong-error.s23 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
33 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
H A Dvalid.s11 add.d $f1,$f7,$f29
40 c.ngl.d $f29,$f29
60 … cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
85 div.d $f29,$f20,$f27
/llvm-project-15.0.7/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips5-wrong-error.s23 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
33 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/compiler-rt/lib/builtins/ppc/
H A DsaveFP.S35 stfd f29,-24(r1)
H A DrestFP.S37 lfd f29,-24(r1)
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Dnumeric-reg-names-f.s152 # CHECK-NUMERIC: fsqrt.s f10, f29
153 # CHECK-NUMERIC-NEXT: fsqrt.s f10, f29
154 fsqrt.s fa0, f29
H A Dnumeric-reg-names-d.s152 # CHECK-NUMERIC: fsqrt.d f10, f29
153 # CHECK-NUMERIC-NEXT: fsqrt.d f10, f29
154 fsqrt.d fa0, f29
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl-old/
H A Dtsan_ppc_regs.h62 #define f29 29 macro
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl/
H A Dtsan_ppc_regs.h62 #define f29 29 macro
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64/
H A Dvalid-mips64-xfail.txt46 0x46 0xdd 0x29 0x33 # CHECK: c.ueq.ps $fcc1, $f5, $f29
62 0x4d 0xd1 0xeb 0x2e # CHECK: msub.ps $f12, $f14, $f29, $f17
73 0x46 0xdd 0xd0 0x6d # CHECK: plu.ps $f1, $f26, $f29
/llvm-project-15.0.7/llvm/test/Bitcode/
H A Dattributes-3.3.ll174 define void @f29() sanitize_memory
175 ; CHECK: define void @f29() #19
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Daarch64-mangle-sve-vectors.cpp70 void f29(S<__clang_svuint16x3_t>) {} in f29() function

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