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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Dcallee-saved-float.ll28 …~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{…
68 ; O32-INV-NOT: sdc1 $f27,
87 ; N32-INV-NOT: sdc1 $f27,
100 ; N64-DAG: sdc1 [[F27:\$f27]], [[OFF27:[0-9]+]]($sp)
H A Dcallee-saved-fpxx.ll13 …~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{…
41 ; O32-FPXX-INV-NOT: sdc1 $f27,
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dno-odd-spreg-msa.ll26 …~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{…
60 …~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{…
90 …~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{…
118 …~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{…
H A Dno-odd-spreg.ll32 …~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{…
56 …~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{…
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dsymbol-variants.s89 .word f27(prel31)-.
91 @CHECK: 6c R_ARM_PREL31 f27
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-csr-alloc.ll20 …1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23…
27 …1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23…
H A Dvsx-spill.ll21 …6},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f3…
54 …6},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f3…
85 …6},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f3…
H A Dspill-vec-pair.ll26 ; CHECK-NEXT: stfd f27, 360(r1) # 8-byte Folded Spill
66 ; CHECK-NEXT: lfd f27, 360(r1) # 8-byte Folded Reload
99 ; CHECK-BE-NEXT: stfd f27, 376(r1) # 8-byte Folded Spill
139 ; CHECK-BE-NEXT: lfd f27, 376(r1) # 8-byte Folded Reload
H A Dcsr-save-restore-order.ll41 ; CHECK-PWR9-NEXT: .cfi_offset f27, -40
101 ; CHECK-PWR9-NEXT: stfd f27, 488(r1) # 8-byte Folded Spill
130 ; CHECK-PWR9-NEXT: lfd f27, 488(r1) # 8-byte Folded Reload
165 …6},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f3…
/llvm-project-15.0.7/compiler-rt/lib/builtins/ppc/
H A DsaveFP.S33 stfd f27,-40(r1)
H A DrestFP.S35 lfd f27,-40(r1)
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Dnumeric-reg-names-f.s142 # CHECK-NUMERIC: fsqrt.s f10, f27
143 # CHECK-NUMERIC-NEXT: fsqrt.s f10, f27
144 fsqrt.s fa0, f27
H A Dnumeric-reg-names-d.s142 # CHECK-NUMERIC: fsqrt.d f10, f27
143 # CHECK-NUMERIC-NEXT: fsqrt.d f10, f27
144 fsqrt.d fa0, f27
H A Drv32d-valid.s15 fadd.s f26, f27, f28
64 fadd.d f26, f27, f28, dyn
139 fadd.d f26, f27, f28, rmm
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r2/
H A Dvalid.s12 … add.ps $f25,$f27,$f13 # CHECK: add.ps $f25, $f27, $f13 # encoding: [0x46,0xcd,0xde,0x40]
137 div.d $f29,$f20,$f27
237 mfc1 $a3,$f27
243 mov.s $f2,$f27
252 movn.d $f27,$f21,$k0
281 neg.d $f27,$f18
319 … round.w.s $f27,$f28 # CHECK: round.w.s $f27, $f28 # encoding: [0x46,0x00,0xe6,0xcc]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips3/
H A Dvalid.s85 div.d $f29,$f20,$f27
160 mfc1 $a3,$f27
165 mov.s $f2,$f27
184 neg.d $f27,$f18
196 … round.w.s $f27,$f28 # CHECK: round.w.s $f27, $f28 # encoding: [0x46,0x00,0xe6,0xcc]
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl-old/
H A Dtsan_ppc_regs.h60 #define f27 27 macro
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl/
H A Dtsan_ppc_regs.h60 #define f27 27 macro
/llvm-project-15.0.7/llvm/test/Bitcode/
H A Dattributes-3.3.ll164 define void @f27() sanitize_address
165 ; CHECK: define void @f27() #17
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64/
H A Dvalid.s122 div.d $f29,$f20,$f27
209 mfc1 $a3,$f27
214 mov.s $f2,$f27
223 movn.d $f27,$f21,$k0
251 neg.d $f27,$f18
270 … round.w.s $f27,$f28 # CHECK: round.w.s $f27, $f28 # encoding: [0x46,0x00,0xe6,0xcc]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips4/
H A Dvalid.s117 div.d $f29,$f20,$f27
196 mfc1 $a3,$f27
201 mov.s $f2,$f27
210 movn.d $f27,$f21,$k0
234 neg.d $f27,$f18
253 … round.w.s $f27,$f28 # CHECK: round.w.s $f27, $f28 # encoding: [0x46,0x00,0xe6,0xcc]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips5/
H A Dvalid.s117 div.d $f29,$f20,$f27
197 mfc1 $a3,$f27
202 mov.s $f2,$f27
211 movn.d $f27,$f21,$k0
235 neg.d $f27,$f18
254 … round.w.s $f27,$f28 # CHECK: round.w.s $f27, $f28 # encoding: [0x46,0x00,0xe6,0xcc]
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Daarch64-mangle-sve-vectors.cpp66 void f27(S<__clang_svuint8x4_t>) {} in f27() function
/llvm-project-15.0.7/llvm/test/MC/Mips/mips2/
H A Dvalid.s98 mfc1 $a3,$f27
104 mov.s $f2,$f27
133 … round.w.s $f27,$f28 # CHECK: round.w.s $f27, $f28 # encoding: [0x46,0x00,0xe6,0xcc]
/llvm-project-15.0.7/llvm/test/MC/PowerPC/
H A Dppc64-regs.s67 #CHECK: .cfi_offset f27, 524
184 .cfi_offset f27,524

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