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/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r3/
H A Dvalid-fp64-el.txt20 0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26
24 0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28
27 0x00 0x71 0xda 0x46 # CHECK: add.ps $f4, $f14, $f26
28 0x02 0x71 0xda 0x46 # CHECK: mul.ps $f4, $f14, $f26
29 0x01 0x71 0xda 0x46 # CHECK: sub.ps $f4, $f14, $f26
H A Dvalid-fp64.txt20 0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
24 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
27 0x46 0xda 0x71 0x00 # CHECK: add.ps $f4, $f14, $f26
28 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
29 0x46 0xda 0x71 0x02 # CHECK: mul.ps $f4, $f14, $f26
H A Dvalid-xfail-mips32r3.txt37 0x46 0xda 0x10 0x3d # CHECK: c.nge.ps $f2, $f26
48 0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
55 0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
56 0x46 0x20 0x36 0x8b # CHECK: floor.l.d $f26, $f6
66 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
69 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
70 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
76 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r5/
H A Dvalid-fp64-el.txt20 0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26
24 0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28
27 0x00 0x71 0xda 0x46 # CHECK: add.ps $f4, $f14, $f26
28 0x02 0x71 0xda 0x46 # CHECK: mul.ps $f4, $f14, $f26
29 0x01 0x71 0xda 0x46 # CHECK: sub.ps $f4, $f14, $f26
H A Dvalid-fp64.txt20 0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
24 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
27 0x46 0xda 0x71 0x00 # CHECK: add.ps $f4, $f14, $f26
28 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
29 0x46 0xda 0x71 0x02 # CHECK: mul.ps $f4, $f14, $f26
H A Dvalid-xfail-mips32r5.txt37 0x46 0xda 0x10 0x3d # CHECK: c.nge.ps $f2, $f26
48 0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
55 0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
56 0x46 0x20 0x36 0x8b # CHECK: floor.l.d $f26, $f6
66 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
69 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
70 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
76 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r2/
H A Dvalid-fp64-el.txt20 0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26
24 0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28
27 0x00 0x71 0xda 0x46 # CHECK: add.ps $f4, $f14, $f26
28 0x02 0x71 0xda 0x46 # CHECK: mul.ps $f4, $f14, $f26
29 0x01 0x71 0xda 0x46 # CHECK: sub.ps $f4, $f14, $f26
H A Dvalid-fp64.txt20 0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
24 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
27 0x46 0xda 0x71 0x00 # CHECK: add.ps $f4, $f14, $f26
28 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
29 0x46 0xda 0x71 0x02 # CHECK: mul.ps $f4, $f14, $f26
H A Dvalid-xfail-mips32r2.txt37 0x46 0xda 0x10 0x3d # CHECK: c.nge.ps $f2, $f26
48 0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
55 0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
56 0x46 0x20 0x36 0x8b # CHECK: floor.l.d $f26, $f6
66 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
69 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
70 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
76 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r2/
H A Dvalid-xfail-mips64r2.txt36 0x46 0xda 0x10 0x3d # CHECK: c.nge.ps $f2, $f26
47 0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
49 0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
50 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
61 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
65 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
66 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r3/
H A Dvalid-xfail-mips64r3.txt36 0x46 0xda 0x10 0x3d # CHECK: c.nge.ps $f2, $f26
47 0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
49 0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
50 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
61 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
65 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
66 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r5/
H A Dvalid-xfail-mips64r5.txt36 0x46 0xda 0x10 0x3d # CHECK: c.nge.ps $f2, $f26
47 0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
49 0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
50 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
61 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
65 0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
66 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
/llvm-project-15.0.7/llvm/test/MC/Mips/mips4/
H A Dinvalid-mips5.s16 …plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
17 …pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
19 …sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
H A Dinvalid-mips5-wrong-error.s15 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
26 c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips5.s17 …plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
18 …pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
20 …sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64/
H A Dvalid-mips64-xfail.txt38 0x46 0xda 0x08 0x3d # CHECK: c.nge.ps $f1, $f26
49 0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
53 0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20
73 0x46 0xdd 0xd0 0x6d # CHECK: plu.ps $f1, $f26, $f29
74 0x46 0xda 0xf2 0x6e # CHECK: pul.ps $f9, $f30, $f26
76 0x46 0xda 0x71 0x41 # CHECK: sub.ps $f5, $f14, $f26
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r3/
H A Dvalid.s90 … cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
96 … cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
110 … cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0]
185 floor.l.d $f26,$f7
286 … pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
288 …plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
291 … pul.ps $f9,$f30,$f26 # CHECK: pul.ps $f9, $f30, $f26 # encoding: [0x46,0xda,0xf2,0x6e]
397 … sub.ps $f5,$f14,$f26 # CHECK: sub.ps $f5, $f14, $f26 # encoding: [0x46,0xda,0x71,0x41]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r2/
H A Dvalid.s91 … cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
97 … cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
111 … cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0]
192 floor.l.d $f26,$f7
293 … pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
295 …plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
298 … pul.ps $f9,$f30,$f26 # CHECK: pul.ps $f9, $f30, $f26 # encoding: [0x46,0xda,0xf2,0x6e]
410 … sub.ps $f5,$f14,$f26 # CHECK: sub.ps $f5, $f14, $f26 # encoding: [0x46,0xda,0x71,0x41]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r5/
H A Dvalid.s90 … cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
96 … cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
110 … cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0]
186 floor.l.d $f26,$f7
288 … pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
290 …plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
293 … pul.ps $f9,$f30,$f26 # CHECK: pul.ps $f9, $f30, $f26 # encoding: [0x46,0xda,0xf2,0x6e]
403 … sub.ps $f5,$f14,$f26 # CHECK: sub.ps $f5, $f14, $f26 # encoding: [0x46,0xda,0x71,0x41]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Dcallee-saved-float.ll28 …~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{…
60 ; O32-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp)
79 ; N32-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp)
99 ; N64-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dno-odd-spreg-msa.ll26 …~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{…
60 …~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{…
90 …~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{…
118 …~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{…
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips1/
H A Dvalid-mips1-el.txt34 0xa1 0x5e 0x80 0x46 # CHECK: cvt.d.w $f26, $f11
35 0xa0 0x46 0x20 0x46 # CHECK: cvt.s.d $f26, $f8
40 0x03 0xa7 0x3a 0x46 # CHECK: div.d $f28, $f20, $f26
77 0x87 0x96 0x20 0x46 # CHECK: neg.d $f26, $f18
H A Dvalid-mips1.txt85 0x46 0x20 0x46 0xa0 # CHECK: cvt.s.d $f26, $f8
88 0x46 0x20 0x96 0x87 # CHECK: neg.d $f26, $f18
94 0x46 0x3a 0xa7 0x03 # CHECK: div.d $f28, $f20, $f26
97 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dsymbol-variants.s88 .word f26(PREL31)-.
90 @CHECK: 68 R_ARM_PREL31 f26
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-csr-alloc.ll20 … $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22…
27 … $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22…

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