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/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r3/
H A Dvalid-xfail-mips32r3.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
32 0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
62 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
66 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
68 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
71 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r5/
H A Dvalid-xfail-mips32r5.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
32 0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
62 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
66 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
68 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
71 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r2/
H A Dvalid-xfail-mips32r2.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
32 0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
62 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
66 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
68 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
71 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r2/
H A Dvalid-xfail-mips64r2.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
55 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
61 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
64 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
67 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r3/
H A Dvalid-xfail-mips64r3.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
55 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
61 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
64 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
67 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r5/
H A Dvalid-xfail-mips64r5.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
55 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
61 0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
64 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
67 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32/
H A Dvalid-xfail-mips32.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32/
H A Dvalid.s15 add.s $f8,$f21,$f24
48 …c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0…
52 …c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0…
61 …c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0…
71 …c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0…
73 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
76 …c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0…
77 …c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0…
79 … ceil.w.d $f11,$f24 # CHECK: ceil.w.d $f11, $f24 # encoding: [0x46,0x20,0xc2,0xce]
98 cvt.w.s $f20,$f24
H A Dinvalid-mips32r2.s8 …cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
19 …mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
26 …nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r5/
H A Dvalid.s15 add.s $f8,$f21,$f24
48 …c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0…
52 …c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0…
61 …c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0…
71 …c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0…
73 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
76 …c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0…
79 … ceil.w.d $f11,$f24 # CHECK: ceil.w.d $f11, $f24 # encoding: [0x46,0x20,0xc2,0xce]
93 cvt.l.d $f24,$f15
100 cvt.w.s $f20,$f24
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s15 add.s $f8,$f21,$f24
48 …c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0…
52 …c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0…
61 …c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0…
71 …c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0…
73 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
76 …c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0…
79 … ceil.w.d $f11, $f24 # CHECK: ceil.w.d $f11, $f24 # encoding: [0x46,0x20,0xc2,0xce]
93 cvt.l.d $f24,$f15
100 cvt.w.s $f20,$f24
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r3/
H A Dvalid.s15 add.s $f8,$f21,$f24
48 …c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0…
52 …c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0…
61 …c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0…
71 …c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0…
73 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
76 …c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0…
79 … ceil.w.d $f11,$f24 # CHECK: ceil.w.d $f11, $f24 # encoding: [0x46,0x20,0xc2,0xce]
93 cvt.l.d $f24,$f15
100 cvt.w.s $f20,$f24
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64/
H A Dvalid.s12 add.s $f8,$f21,$f24
45 …c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0…
49 …c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0…
58 …c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0…
68 …c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0…
70 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
73 …c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0…
74 …c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0…
92 … cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
104 … cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips4/
H A Dvalid.s12 add.s $f8,$f21,$f24
45 …c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0…
49 …c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0…
58 …c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0…
68 …c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0…
70 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
73 …c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0…
74 …c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0…
90 … cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
102 … cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips5/
H A Dvalid.s12 add.s $f8,$f21,$f24
45 …c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0…
49 …c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0…
58 …c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0…
68 …c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0…
70 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
73 …c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0…
74 …c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0…
90 … cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
102 … cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r3/
H A Dvalid.s12 add.s $f8,$f21,$f24
45 …c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0…
49 …c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0…
58 …c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0…
68 …c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0…
70 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
92 … cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
104 … cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
231 mfhc1 $s8,$f24
277 nmsub.s $f1,$f24,$f19,$f4
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r2/
H A Dvalid.s13 add.s $f8,$f21,$f24
46 …c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0…
50 …c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0…
59 …c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0…
69 …c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0…
71 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
93 … cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
105 … cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
238 mfhc1 $s8,$f24
284 nmsub.s $f1,$f24,$f19,$f4
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r5/
H A Dvalid.s12 add.s $f8,$f21,$f24
45 …c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0…
49 …c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0…
58 …c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0…
68 …c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0…
70 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
92 … cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
104 … cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
233 mfhc1 $s8,$f24
279 nmsub.s $f1,$f24,$f19,$f4
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64/
H A Dvalid-mips64-xfail.txt4 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
8 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
15 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
28 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
71 0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
75 0x46 0xc2 0x4e 0x2f # CHECK: puu.ps $f24, $f9, $f2
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips/
H A Dvalid.s325 c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x56,0x38,0xa0,0xbc]
329 c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x54,0x98,0xc3,0xbc]
338 c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x54,0xd8,0x87,0xfc]
348 c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x57,0x0c,0x84,0xfc]
350 c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x56,0x58,0xe5,0xfc]
353 c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x55,0x58,0xe1,0x7c]
354 c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x57,0x16,0xc4,0x7c]
/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/Mips/
H A Dlive-debug-values-reg-copy.mir12 # CHECK: DBG_VALUE $f24, $noreg, ![[ARG1]], !DIExpression(), debug-location
13 # CHECK: $f26 = FMOV_S killed $f24, debug-location
225 renamable $f24 = FADD_S killed renamable $f12, killed renamable $f0, debug-location !19
226 DBG_VALUE $f24, $noreg, !14, !DIExpression(), debug-location !19
227 $f12 = COPY renamable $f24, debug-location !19
233 $f12 = COPY renamable $f24, debug-location !19
238 $f26 = FMOV_S killed $f24, debug-location !19
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Dcallee-saved-float.ll28 …~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{…
59 ; O32-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)
78 ; N32-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)
97 ; N64-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dno-odd-spreg-msa.ll26 …~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{…
60 …~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{…
90 …~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{…
118 …~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{…
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dsymbol-variants.s82 .word f24(TLSDESC)
84 @ CHECK: 60 R_ARM_TLS_GOTDESC f24
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-csr-alloc.ll20 …f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20…
27 …f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20…

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