Home
last modified time | relevance | path

Searched refs:f23 (Results 1 – 25 of 173) sorted by relevance

1234567

/llvm-project-15.0.7/llvm/test/MC/Mips/mips3d/
H A Dvalid.s7 mulr.ps $f23, $f5, $f1 # CHECK: mulr.ps $f23, $f5, $f1 # encoding: [0x46,0xc1,0x2d,0xda]
/llvm-project-15.0.7/compiler-rt/test/fuzzer/
H A DCallerCalleeTest.cpp20 void f23() { t[(unsigned)'d'] = f34;} in f23() function
21 void f12() { t[(unsigned)'c'] = f23;} in f12()
48 f23(); in LLVMFuzzerTestOneInput()
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32/
H A Dvalid-xfail-mips32.txt13 0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dno-odd-spreg-msa.ll26 …~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{…
60 …~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{…
90 …~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{…
118 …~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{…
H A Dno-odd-spreg.ll32 …~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{…
56 …~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{…
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64/
H A Dvalid.s54 …c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0…
55 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
221 movf.s $f23,$f5,$fcc6
349 sub.s $f23,$f22,$f22
392 … trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips4/
H A Dvalid.s54 …c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0…
55 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
208 movf.s $f23,$f5,$fcc6
330 sub.s $f23,$f22,$f22
372 … trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips5/
H A Dvalid.s54 …c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0…
55 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
209 movf.s $f23,$f5,$fcc6
331 sub.s $f23,$f22,$f22
374 … trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dsymbol-variants.s77 .word f23(tlscall)
79 @ CHECK: 5c R_ARM_TLS_CALL f23
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-csr-alloc.ll20 …6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19…
27 …6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19…
H A Dvsx-spill.ll21 …2},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f2…
54 …2},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f2…
85 …2},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f2…
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r3/
H A Dvalid.s54 …c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0…
55 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
243 movf.s $f23,$f5,$fcc6
398 sub.s $f23,$f22,$f22
443 … trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r2/
H A Dvalid.s55 …c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0…
56 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
250 movf.s $f23,$f5,$fcc6
411 sub.s $f23,$f22,$f22
456 … trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r5/
H A Dvalid.s54 …c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0…
55 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
245 movf.s $f23,$f5,$fcc6
404 sub.s $f23,$f22,$f22
449 … trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips4.s56 …movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
57 …movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
72 …trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/llvm-project-15.0.7/compiler-rt/lib/builtins/ppc/
H A DsaveFP.S29 stfd f23,-72(r1)
H A DrestFP.S31 lfd f23,-72(r1)
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Dnumeric-reg-names-f.s122 # CHECK-NUMERIC: fsqrt.s f10, f23
123 # CHECK-NUMERIC-NEXT: fsqrt.s f10, f23
124 fsqrt.s fa0, f23
H A Dnumeric-reg-names-d.s122 # CHECK-NUMERIC: fsqrt.d f10, f23
123 # CHECK-NUMERIC-NEXT: fsqrt.d f10, f23
124 fsqrt.d fa0, f23
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r2/
H A Dvalid-xfail-mips64r2.txt13 0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r3/
H A Dvalid-xfail-mips64r3.txt13 0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r5/
H A Dvalid-xfail-mips64r5.txt13 0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
29 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dtwoaddr-sink.ll7 define i32 @f23(i32 %old) {
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Dcallee-saved-fpxx.ll13 …~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{…
39 ; O32-FPXX-INV-NOT: sdc1 $f23,
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl-old/
H A Dtsan_ppc_regs.h56 #define f23 23 macro

1234567