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/llvm-project-15.0.7/llvm/test/CodeGen/SPARC/
H A Dinlineasm-v9.ll32 ; CHECK: fadds %f20, %f20, %f20
33 ; CHECK: faddd %f20, %f20, %f20
37 …tail call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"(float 6.0, float 7.0, float 8.…
38 …tail call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"(double 9.0, double 10.0, doubl…
H A Dinlineasm.ll125 ; CHECK: fadds %f20, %f20, %f20
126 ; CHECK: faddd %f20, %f20, %f20
129 …tail call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"(float 6.0, float 7.0, float 8.…
130 …tail call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"(double 9.0, double 10.0, doubl…
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r2/
H A Dvalid-xfail-mips64r2.txt18 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
20 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
34 0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20
38 0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20
40 0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8
50 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
55 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
60 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r3/
H A Dvalid-xfail-mips64r3.txt18 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
20 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
34 0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20
38 0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20
40 0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8
50 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
55 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
60 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r5/
H A Dvalid-xfail-mips64r5.txt18 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
20 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
34 0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20
38 0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20
40 0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8
50 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
55 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
60 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64/
H A Dvalid.s46 …c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0…
52 …c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0…
61 …c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0…
63 …c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0…
80 … ceil.w.s $f6,$f20 # CHECK: ceil.w.s $f6, $f20 # encoding: [0x46,0x00,0xa1,0x8e]
102 … cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
104 … cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
122 div.d $f29,$f20,$f27
206 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
213 mov.d $f20,$f14
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips4/
H A Dvalid.s46 …c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0…
52 …c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0…
61 …c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0…
63 …c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0…
80 … ceil.w.s $f6,$f20 # CHECK: ceil.w.s $f6, $f20 # encoding: [0x46,0x00,0xa1,0x8e]
100 … cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
102 … cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
117 div.d $f29,$f20,$f27
194 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
200 mov.d $f20,$f14
[all …]
H A Dinvalid-mips5-wrong-error.s13 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
31 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/MC/Mips/mips5/
H A Dvalid.s46 …c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0…
52 …c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0…
61 …c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0…
63 …c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0…
80 … ceil.w.s $f6,$f20 # CHECK: ceil.w.s $f6, $f20 # encoding: [0x46,0x00,0xa1,0x8e]
100 … cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
102 … cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
117 div.d $f29,$f20,$f27
195 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
201 mov.d $f20,$f14
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r3/
H A Dvalid.s46 …c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0…
52 …c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0…
61 …c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0…
63 …c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0…
80 … ceil.w.s $f6,$f20 # CHECK: ceil.w.s $f6, $f20 # encoding: [0x46,0x00,0xa1,0x8e]
102 … cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
104 … cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
106 …cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
130 div.d $f29,$f20,$f27
235 mov.d $f20,$f14
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r2/
H A Dvalid.s47 …c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0…
53 …c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0…
62 …c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0…
64 …c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0…
81 … ceil.w.s $f6,$f20 # CHECK: ceil.w.s $f6, $f20 # encoding: [0x46,0x00,0xa1,0x8e]
103 … cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
105 … cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
107 …cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
137 div.d $f29,$f20,$f27
242 mov.d $f20,$f14
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r5/
H A Dvalid.s46 …c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0…
52 …c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0…
61 …c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0…
63 …c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0…
80 … ceil.w.s $f6,$f20 # CHECK: ceil.w.s $f6, $f20 # encoding: [0x46,0x00,0xa1,0x8e]
102 … cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
104 … cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
106 …cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
130 div.d $f29,$f20,$f27
237 mov.d $f20,$f14
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r3/
H A Dvalid-xfail-mips32r3.txt18 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
20 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
35 0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20
39 0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20
41 0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
62 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r5/
H A Dvalid-xfail-mips32r5.txt18 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
20 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
35 0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20
39 0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20
41 0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
62 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r2/
H A Dvalid-xfail-mips32r2.txt18 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
20 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
35 0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20
39 0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20
41 0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
62 0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
/llvm-project-15.0.7/llvm/test/MC/Mips/mips3d/
H A Dvalid.s6 cvt.pw.ps $f5, $f20 # CHECK: cvt.pw.ps $f5, $f20 # encoding: [0x46,0xc0,0xa1,0x64]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfp-intrinsics-fptosi-legal.ll9 ; CHECK-LABEL: @f20
11 define i32 @f20(double %a) strictfp {
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64/
H A Dvalid-mips64-xfail.txt18 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
20 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
36 0x46 0xd4 0x39 0x3e # CHECK: c.le.ps $fcc1, $f7, $f20
40 0x46 0xd4 0x67 0x39 # CHECK: c.ngle.ps $fcc7, $f12, $f20
53 0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20
59 0x46 0xc9 0xcd 0x11 # CHECK: movt.ps $f20, $f25, $fcc2
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips1/
H A Dvalid-mips1-el.txt37 0x24 0x75 0x20 0x46 # CHECK: cvt.w.d $f20, $f14
38 0x24 0xc5 0x00 0x46 # CHECK: cvt.w.s $f20, $f24
40 0x03 0xa7 0x3a 0x46 # CHECK: div.d $f28, $f20, $f26
59 0x06 0x75 0x20 0x46 # CHECK: mov.d $f20, $f14
69 0x02 0xa5 0x30 0x46 # CHECK: mul.d $f20, $f20, $f16
H A Dvalid-mips1.txt77 0x46 0x00 0xc5 0x24 # CHECK: cvt.w.s $f20, $f24
86 0x46 0x20 0x75 0x06 # CHECK: mov.d $f20, $f14
87 0x46 0x20 0x75 0x24 # CHECK: cvt.w.d $f20, $f14
93 0x46 0x30 0xa5 0x02 # CHECK: mul.d $f20, $f20, $f16
94 0x46 0x3a 0xa7 0x03 # CHECK: div.d $f28, $f20, $f26
/llvm-project-15.0.7/llvm/test/MC/Mips/mips3/
H A Dinvalid-mips5-wrong-error.s13 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
31 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips5-wrong-error.s13 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
31 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips2/
H A Dvalid-mips2-el.txt39 0x8e 0xa1 0x00 0x46 # CHECK: ceil.w.s $f6, $f20
46 0x24 0x75 0x20 0x46 # CHECK: cvt.w.d $f20, $f14
47 0x24 0xc5 0x00 0x46 # CHECK: cvt.w.s $f20, $f24
49 0x03 0xa7 0x3a 0x46 # CHECK: div.d $f28, $f20, $f26
75 0x06 0x75 0x20 0x46 # CHECK: mov.d $f20, $f14
85 0x02 0xa5 0x30 0x46 # CHECK: mul.d $f20, $f20, $f16
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32/
H A Dvalid.s49 …c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0…
55 …c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0…
64 …c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0…
66 …c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0…
81 … ceil.w.s $f6,$f20 # CHECK: ceil.w.s $f6, $f20 # encoding: [0x46,0x00,0xa1,0x8e]
98 cvt.w.s $f20,$f24
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Dcallee-saved-fpxx1.ll22 ; O32-FP64-INV-NOT: sdc1 $f20,
23 ; O32-FPXX-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)

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