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/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips32r2.s9 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
10 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
12 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
13 …nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
16 …nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
H A Dinvalid-mips5.s8 …luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32/
H A Dinvalid-mips32r2.s15 …luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
17 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
18 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
21 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
23 …nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
26 …nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
35 …swxc1 $f19,$t4($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64/
H A Dvalid-mips64-xfail.txt19 0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
37 0x46 0xc5 0x98 0x3c # CHECK: c.lt.ps $f19, $f5
50 0x46 0x13 0x90 0xe6 # CHECK: cvt.ps.s $f3, $f18, $f19
53 0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20
55 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
63 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
65 0x46 0xc0 0x6c 0xc7 # CHECK: neg.ps $f19, $f13
66 0x4d 0x33 0x74 0xb1 # CHECK: nmadd.d $f18, $f9, $f14, $f19
71 0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/modernize/
H A Dreturn-braced-init-list.cpp162 T f19() { in f19() function
166 Bar i1 = f19<Bar>();
167 Baz i2 = f19<Baz>();
H A Duse-nodiscard.cpp111 bool f19() const;
188 bool Foo::f19() const { in f19() function in Foo
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dset-mips-directives.s15 luxc1 $f19,$2($4)
51 # CHECK: luxc1 $f19, $2($4)
H A Dset-arch.s14 luxc1 $f19, $2($4)
55 # CHECK: luxc1 $f19, $2($4)
/llvm-project-15.0.7/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips32r2.s53 …luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
57 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
58 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
82 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
87 …nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
90 …nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
99 …swxc1 $f19,$t4($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
H A Dinvalid-mips5-wrong-error.s14 c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
34 neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-csr.ll100 call void asm sideeffect "", "~{r13},~{r14},~{r25},~{r31},~{f14},~{f19},~{f21},~{f31}"()
114 ; MIR64-NEXT: callee-saved-register: '$f19', callee-saved-restored: true, debug-info-variabl…
139 ; MIR32-NEXT: callee-saved-register: '$f19', callee-saved-restored: true, debug-info-variabl…
159 ; MIR64: liveins: $x3, $x14, $x25, $x31, $f14, $f19, $f21, $f31
168 ; MIR64-DAG: STFD killed $f19, 296, $x1 :: (store (s64) into %fixed-stack.2)
177 ; MIR64-DAG: $f19 = LFD 296, $x1 :: (load (s64) from %fixed-stack.2)
188 ; MIR32: liveins: $r3, $r13, $r14, $r25, $r31, $f14, $f19, $f21, $f31
198 ; MIR32-DAG: STFD killed $f19, 184, $r1 :: (store (s64) into %fixed-stack.2)
207 ; MIR32-DAG: $f19 = LFD 184, $r1 :: (load (s64) from %fixed-stack.2)
H A Daix-csr-alloc.ll20 …f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15…
27 …f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15…
H A Dvsx-spill.ll21 …f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f2…
54 …f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f2…
85 …f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f2…
/llvm-project-15.0.7/clang/test/CXX/dcl/dcl.fct/
H A Dp17.cpp228 void f19(C2<char> auto &... x);
230 static_assert(is_same_v<decltype(f19(c, c)), void>);
231 static_assert(is_same_v<decltype(f19(i, c)), void>);
233 static_assert(is_same_v<decltype(f19(c, c, cc)), void>);
/llvm-project-15.0.7/llvm/test/MC/Mips/mips4/
H A Dinvalid-mips5.s9 …luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
11 …cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
H A Dinvalid-mips5-wrong-error.s14 c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
34 neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dno-odd-spreg-msa.ll26 …},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{…
60 …},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{…
90 …},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{…
118 …,~{$f9},~{$f10},~{$f11},~{$f12},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{…
/llvm-project-15.0.7/compiler-rt/lib/xray/
H A Dxray_trampoline_mips64.S36 sdc1 $f19, 56($sp)
69 ldc1 $f19, 56($sp)
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dsymbol-variants.s65 .word f19(prel31)
67 @CHECK: 4c R_ARM_PREL31 f19
/llvm-project-15.0.7/llvm/test/MC/Mips/mips3/
H A Dinvalid-mips5-wrong-error.s14 c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
34 neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips5-wrong-error.s17 … c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 … neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/llvm-project-15.0.7/compiler-rt/lib/builtins/ppc/
H A DsaveFP.S25 stfd f19,-104(r1)
H A DrestFP.S27 lfd f19,-104(r1)
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Dnumeric-reg-names-f.s102 # CHECK-NUMERIC: fsqrt.s f10, f19
103 # CHECK-NUMERIC-NEXT: fsqrt.s f10, f19
104 fsqrt.s fa0, f19
H A Dnumeric-reg-names-d.s102 # CHECK-NUMERIC: fsqrt.d f10, f19
103 # CHECK-NUMERIC-NEXT: fsqrt.d f10, f19
104 fsqrt.d fa0, f19

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