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Searched refs:f18 (Results 1 – 25 of 264) sorted by relevance

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/llvm-project-15.0.7/flang/tools/f18-parse-demo/
H A DCMakeLists.txt7 add_flang_tool(f18-parse-demo
8 f18-parse-demo.cpp
12 target_link_libraries(f18-parse-demo
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r2/
H A Dvalid-xfail-mips64r2.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
35 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
56 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
57 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
59 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
60 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r3/
H A Dvalid-xfail-mips64r3.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
35 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
56 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
57 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
59 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
60 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r5/
H A Dvalid-xfail-mips64r5.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
35 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
56 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
57 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
59 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
60 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
/llvm-project-15.0.7/clang/test/CXX/dcl/dcl.fct/
H A Dp17.cpp87 void f18(auto... x) requires (sizeof...(x) == 2);
92 static_assert(is_same_v<decltype(f18('c')), void>);
94 static_assert(is_same_v<decltype(f18('c', 1)), void>);
95 static_assert(is_same_v<decltype(f18('c', 1, 2)), void>);
221 void f18(C2<char> auto... x);
223 static_assert(is_same_v<decltype(f18('a', 'b')), void>);
224 static_assert(is_same_v<decltype(f18('a', 1)), void>);
226 static_assert(is_same_v<decltype(f18(2, 'a')), void>);
/llvm-project-15.0.7/flang/tools/f18/
H A DCMakeLists.txt42 add_custom_command(OUTPUT ${base}.f18.mod
44 COMMAND ${CMAKE_COMMAND} -E copy ${base}.mod ${base}.f18.mod)
45 list(APPEND MODULE_FILES ${base}.mod ${base}.f18.mod)
46 install(FILES ${base}.mod ${base}.f18.mod DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}/flang")
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64/
H A Dvalid-mips64-xfail.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
33 0x4d 0x9e 0x93 0x1e # CHECK: alnv.ps $f12, $f18, $f30, $8
50 0x46 0x13 0x90 0xe6 # CHECK: cvt.ps.s $f3, $f18, $f19
53 0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20
60 0x46 0xdf 0x8c 0x92 # CHECK: movz.ps $f18, $f17, ra
61 0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18
66 0x4d 0x33 0x74 0xb1 # CHECK: nmadd.d $f18, $f9, $f14, $f19
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r3/
H A Dvalid-xfail-mips32r3.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
63 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
65 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r5/
H A Dvalid-xfail-mips32r5.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
63 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
65 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r2/
H A Dvalid-xfail-mips32r2.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
63 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
65 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
/llvm-project-15.0.7/flang/
H A D.drone.star11 … "git clone --depth=1 -b f18 https://github.com/flang-compiler/f18-llvm-project.git llvm-project",
37 … "git clone --depth=1 -b f18 https://github.com/flang-compiler/f18-llvm-project.git llvm-project",
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips32r2.s9 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
11 …msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
13 …nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/llvm-project-15.0.7/flang/tools/
H A DCMakeLists.txt10 add_subdirectory(f18)
13 add_subdirectory(f18-parse-demo)
/llvm-project-15.0.7/llvm/test/MC/Mips/mips3d/
H A Dvalid.s5 cvt.ps.pw $f3, $f18 # CHECK: cvt.ps.pw $f3, $f18 # encoding: [0x46,0x80,0x90,0xe6]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64/
H A Dvalid.s48 …c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0…
55 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
62 …c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0…
70 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
77 ceil.l.s $f18,$f13
206 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
207 madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
233 msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
234 msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
251 neg.d $f27,$f18
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips4/
H A Dvalid.s48 …c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0…
55 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
62 …c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0…
70 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
77 ceil.l.s $f18,$f13
194 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
218 msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
219 msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
234 neg.d $f27,$f18
236 nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips5/
H A Dvalid.s48 …c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0…
55 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
62 …c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0…
70 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
77 ceil.l.s $f18,$f13
195 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
196 madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
219 msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
220 msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
235 neg.d $f27,$f18
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32/
H A Dvalid-xfail-mips32.txt7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r5/
H A Dvalid.s51 …c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0…
58 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
65 …c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0…
73 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
148 madd.d $f18,$f19,$f26,$f20
177 msub.d $f10,$f1,$f31,$f18
202 nmadd.d $f18,$f9,$f14,$f19
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s51 …c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0…
58 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
65 …c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0…
73 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
147 madd.d $f18,$f19,$f26,$f20
176 msub.d $f10,$f1,$f31,$f18
201 nmadd.d $f18,$f9,$f14,$f19
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r3/
H A Dvalid.s51 …c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0…
58 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
65 …c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0…
73 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
147 madd.d $f18,$f19,$f26,$f20
176 msub.d $f10,$f1,$f31,$f18
201 nmadd.d $f18,$f9,$f14,$f19
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r3/
H A Dvalid.s48 …c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0…
55 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
62 …c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0…
70 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
77 ceil.l.s $f18,$f13
106 …cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
274 neg.d $f27,$f18
396 sub.d $f18,$f3,$f17
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r2/
H A Dvalid.s49 …c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0…
56 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
63 …c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0…
71 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
78 ceil.l.s $f18,$f13
107 …cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
281 neg.d $f27,$f18
409 sub.d $f18,$f3,$f17
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r5/
H A Dvalid.s48 …c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0…
55 …c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0…
62 …c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0…
70 …c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0…
77 ceil.l.s $f18,$f13
106 …cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
276 neg.d $f27,$f18
402 sub.d $f18,$f3,$f17
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dfastcc.ll178 ; CHECK: lwc1 $f18
244 ; CHECK-DAG: swc1 $f18
277 ; f0, f2, ... , f18. Check that 11th argument is passed on stack.
289 ; NOODDSPREG-DAG: lwc1 $f18, 36($[[R0]])
319 ; f0, f2, ... , f18. Check that 11th argument is received on stack.
331 ; NOODDSPREG-DAG: swc1 $f18, 36($[[R0]])
356 ; f0, f2, ... , f18. Check that 11th argument is passed on stack.
368 ; FP64-NOODDSPREG-DAG: ldc1 $f18, 72($[[R0]])
399 ; f0, f2, ... , f18. Check that 11th argument is received on stack.
411 ; FP64-NOODDSPREG-DAG: sdc1 $f18, 72($[[R0]])

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