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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A D2013-04-18-load-overlap-PR14824.ll17 %data.i.i677.48.extract.trunc = trunc i512 %data.i.i677.48.extract.shift to i64
20 %data.i.i677.32.extract.trunc = trunc i512 %data.i.i677.32.extract.shift to i64
23 %data.i.i677.16.extract.trunc = trunc i512 %data.i.i677.16.extract.shift to i64
26 %data.i.i677.56.extract.trunc = trunc i512 %data.i.i677.56.extract.shift to i64
29 %data.i.i677.24.extract.trunc = trunc i512 %data.i.i677.24.extract.shift to i64
41 %data.i1.i676.48.extract.trunc = trunc i512 %data.i1.i676.48.extract.shift to i64
44 %data.i1.i676.32.extract.trunc = trunc i512 %data.i1.i676.32.extract.shift to i64
47 %data.i1.i676.16.extract.trunc = trunc i512 %data.i1.i676.16.extract.shift to i64
50 %data.i1.i676.56.extract.trunc = trunc i512 %data.i1.i676.56.extract.shift to i64
53 %data.i1.i676.24.extract.trunc = trunc i512 %data.i1.i676.24.extract.shift to i64
[all …]
H A Dbf16-intrinsics-ld-st.ll71 %0 = bitcast <4 x bfloat> %vld1xN.fca.0.extract to <2 x i32>
72 %1 = bitcast <4 x bfloat> %vld1xN.fca.1.extract to <2 x i32>
87 %0 = bitcast <8 x bfloat> %vld1xN.fca.0.extract to <4 x i32>
88 %1 = bitcast <8 x bfloat> %vld1xN.fca.1.extract to <4 x i32>
104 %0 = bitcast <4 x bfloat> %vld1xN.fca.0.extract to <2 x i32>
105 %1 = bitcast <4 x bfloat> %vld1xN.fca.1.extract to <2 x i32>
106 %2 = bitcast <4 x bfloat> %vld1xN.fca.2.extract to <2 x i32>
124 %0 = bitcast <8 x bfloat> %vld1xN.fca.0.extract to <4 x i32>
125 %1 = bitcast <8 x bfloat> %vld1xN.fca.1.extract to <4 x i32>
126 %2 = bitcast <8 x bfloat> %vld1xN.fca.2.extract to <4 x i32>
[all …]
H A Dha-alignstack.ll14 ret float %s.coerce.fca.0.0.extract
24 ret float %s.coerce.fca.0.0.extract
34 ret float %s.coerce.fca.0.0.extract
44 ret float %s.coerce.fca.0.0.extract
54 ret float %s.coerce.fca.0.0.extract
64 ret float %s.coerce.fca.0.0.extract
74 ret float %s.coerce.fca.0.0.extract
84 ret float %s.coerce.fca.0.0.extract
94 ret float %s.coerce.fca.0.0.extract
104 ret double %s.coerce.fca.0.0.extract
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Daarch64-bf16-ldst-intrinsics.ll645 …6(<4 x bfloat> %val.coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, <4 x bfloat> %va…
661 …6(<8 x bfloat> %val.coerce.fca.0.extract, <8 x bfloat> %val.coerce.fca.1.extract, <8 x bfloat> %va…
679 …coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, <4 x bfloat> %val.coerce.fca.2.extra…
696 …coerce.fca.0.extract, <8 x bfloat> %val.coerce.fca.1.extract, <8 x bfloat> %val.coerce.fca.2.extra…
779 …8(<4 x bfloat> %val.coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, <4 x bfloat> %va…
797 …8(<8 x bfloat> %val.coerce.fca.0.extract, <8 x bfloat> %val.coerce.fca.1.extract, <8 x bfloat> %va…
815 …8(<4 x bfloat> %val.coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, <4 x bfloat> %va…
852 …coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, <4 x bfloat> %val.coerce.fca.2.extra…
871 …coerce.fca.0.extract, <8 x bfloat> %val.coerce.fca.1.extract, <8 x bfloat> %val.coerce.fca.2.extra…
890 …coerce.fca.0.extract, <4 x bfloat> %val.coerce.fca.1.extract, <4 x bfloat> %val.coerce.fca.2.extra…
[all …]
H A Dsve-extract-vector-to-predicate-store.ll11 %extract = tail call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0)
12 store <2 x i8> %extract, <2 x i8>* %addr, align 4
22 %extract = tail call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0)
23 store <4 x i8> %extract, <4 x i8>* %addr, align 4
33 %extract = tail call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0)
34 store <8 x i8> %extract, <8 x i8>* %addr, align 4
42 ; CHECK: call <4 x i8> @llvm.vector.extract
44 %extract = tail call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0)
54 %extract = tail call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 0)
64 %extract = tail call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8(<vscale x 2 x i8> %bitcast, i64 4)
[all …]
H A Dextract-subvec-combine.ll11 %extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 0)
12 %and = and <2 x i32> %extract, <i32 65535, i32 65535>
23 %extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 0)
24 %and = and <4 x i16> %extract, <i16 255, i16 255, i16 255, i16 255>
36 %extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 2)
37 %and = and <2 x i32> %extract, <i32 65535, i32 65535>
49 %extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 4)
50 %and = and <4 x i16> %extract, <i16 255, i16 255, i16 255, i16 255>
54 declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32>, i64)
55 declare <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16>, i64)
H A Dsve-fixed-length-extract-subvector.ll16 %ret = call <4 x i8> @llvm.vector.extract.v4i8.v8i8(<8 x i8> %op, i64 4)
616 declare <4 x i8> @llvm.vector.extract.v4i8.v8i8(<8 x i8>, i64)
617 declare <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8>, i64)
618 declare <16 x i8> @llvm.vector.extract.v16i8.v32i8(<32 x i8>, i64)
619 declare <32 x i8> @llvm.vector.extract.v32i8.v64i8(<64 x i8>, i64)
623 declare <2 x i16> @llvm.vector.extract.v2i16.v4i16(<4 x i16>, i64)
624 declare <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16>, i64)
630 declare <1 x i32> @llvm.vector.extract.v1i32.v2i32(<2 x i32>, i64)
631 declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32>, i64)
632 declare <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32>, i64)
[all …]
H A Darm64-dagcombiner-load-slicing.ll20 %t0.sroa.0.0.extract.trunc = trunc i64 %1 to i32
21 %2 = bitcast i32 %t0.sroa.0.0.extract.trunc to float
22 %t0.sroa.2.0.extract.shift = lshr i64 %1, 32
23 %t0.sroa.2.0.extract.trunc = trunc i64 %t0.sroa.2.0.extract.shift to i32
24 %3 = bitcast i32 %t0.sroa.2.0.extract.trunc to float
52 %t0.sroa.0.0.extract.trunc = trunc i64 %1 to i32
53 %2 = bitcast i32 %t0.sroa.0.0.extract.trunc to i32
54 %t0.sroa.2.0.extract.shift = lshr i64 %1, 32
55 %t0.sroa.2.0.extract.trunc = trunc i64 %t0.sroa.2.0.extract.shift to i32
86 %t0.sroa.2.0.extract.shift = lshr i128 %1, 64
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-extracts.mir42 $x0 = COPY %extract
60 $x0 = COPY %extract
78 $w0 = COPY %extract
96 $w0 = COPY %extract
114 $w0 = COPY %extract
132 $h0 = COPY %extract
150 $h0 = COPY %extract
168 $h0 = COPY %extract
186 $b0 = COPY %extract
204 $b0 = COPY %extract
[all …]
H A Dcombine-extract-vec-elt.mir27 %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32)
28 $x0 = COPY %extract(s64)
57 $x0 = COPY %extract(s64)
83 ; CHECK: $x0 = COPY %extract(s64)
90 $x0 = COPY %extract(s64)
112 ; CHECK: %extract:_(s32) = G_TRUNC %arg1(s64)
113 ; CHECK: $w0 = COPY %extract(s32)
120 $w0 = COPY %extract(s32)
146 ; CHECK: $x0 = COPY %extract(s64)
154 $x0 = COPY %extract(s64)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/mve-intrinsics/
H A Dvld24.ll90 …2.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coerce.fca.0.1.extra…
121 …v8f16(half* %addr, <8 x half> %value.coerce.fca.0.0.extract, <8 x half> %value.coerce.fca.0.1.extr…
122 …v8f16(half* %addr, <8 x half> %value.coerce.fca.0.0.extract, <8 x half> %value.coerce.fca.0.1.extr…
156 …ce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extra…
157 …ce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extra…
158 …ce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extra…
159 …ce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extra…
176 …ce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extra…
177 …ce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extra…
178 …ce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extra…
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dbit-loop.ll19 %v.sroa.4.0.extract.shift = lshr i64 %0, 16
20 %v.sroa.4.0.extract.trunc = trunc i64 %v.sroa.4.0.extract.shift to i16
21 %v.sroa.5.0.extract.shift = lshr i64 %0, 32
22 %v.sroa.5.0.extract.trunc = trunc i64 %v.sroa.5.0.extract.shift to i16
23 %v.sroa.6.0.extract.shift = lshr i64 %0, 48
24 %v.sroa.6.0.extract.trunc = trunc i64 %v.sroa.6.0.extract.shift to i16
42 …%v.sroa.0.157 = phi i16 [ %v.sroa.0.0.extract.trunc34, %for.body ], [ %v.sroa.0.0.extract.trunc, %…
43 …%v.sroa.4.156 = phi i16 [ %v.sroa.4.0.extract.trunc36, %for.body ], [ %v.sroa.4.0.extract.trunc, %…
55 %v.sroa.4.0.extract.trunc36 = trunc i64 %v.sroa.4.0.extract.shift35 to i16
57 %v.sroa.5.0.extract.trunc38 = trunc i64 %v.sroa.5.0.extract.shift37 to i16
[all …]
H A Dswp-copytophi-dag.ll21 %v.sroa.4.0.extract.shift = lshr i64 %tmp, 16
22 %v.sroa.4.0.extract.trunc = trunc i64 %v.sroa.4.0.extract.shift to i16
23 %v.sroa.5.0.extract.shift = lshr i64 %tmp, 32
24 %v.sroa.5.0.extract.trunc = trunc i64 %v.sroa.5.0.extract.shift to i16
25 %v.sroa.6.0.extract.shift = lshr i64 %tmp, 48
26 %v.sroa.6.0.extract.trunc = trunc i64 %v.sroa.6.0.extract.shift to i16
44 …%v.sroa.0.157 = phi i16 [ %v.sroa.0.0.extract.trunc34, %for.body ], [ %v.sroa.0.0.extract.trunc, %…
45 …%v.sroa.4.156 = phi i16 [ %v.sroa.4.0.extract.trunc36, %for.body ], [ %v.sroa.4.0.extract.trunc, %…
57 %v.sroa.4.0.extract.trunc36 = trunc i64 %v.sroa.4.0.extract.shift35 to i16
59 %v.sroa.5.0.extract.trunc38 = trunc i64 %v.sroa.5.0.extract.shift37 to i16
[all …]
H A Dtwo-crash.ll10 %t.sroa.0.0.extract.trunc = trunc i64 %x to i32
11 %t4.sroa.4.0.extract.shift = lshr i64 %x, 16
12 %add11 = add i32 0, %t.sroa.0.0.extract.trunc
13 %t14.sroa.3.0.extract.trunc = trunc i64 %t4.sroa.4.0.extract.shift to i32
14 %t14.sroa.4.0.extract.shift = lshr i64 %x, 24
15 %add21 = add i32 %add11, %t14.sroa.3.0.extract.trunc
16 %t24.sroa.3.0.extract.trunc = trunc i64 %t14.sroa.4.0.extract.shift to i32
17 %add31 = add i32 %add21, %t24.sroa.3.0.extract.trunc
H A Dinsert4.ll23 %h.sroa.0.0.extract.trunc = trunc i64 %c to i32
24 %sext = shl i32 %h.sroa.0.0.extract.trunc, 16
26 %l.sroa.2.4.extract.shift = lshr i64 %c, 32
27 %sext76 = ashr i32 %h.sroa.0.0.extract.trunc, 16
28 %m.sroa.2.6.extract.shift = lshr i64 %c, 48
29 %sext7980 = shl nuw nsw i64 %l.sroa.2.4.extract.shift, 16
43 %n_union3.sroa.0.0.extract.trunc = trunc i64 %1 to i32
44 %n_union3.sroa.1.4.extract.shift = lshr i64 %1, 32
49 %n_union13.sroa.1.4.extract.trunc = trunc i64 %n_union3.sroa.1.4.extract.shift to i32
56 %n_union28.sroa.1.4.extract.shift = lshr i64 %8, 32
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-multi-reduction-outer-lowering.mlir11 // CHECK: %[[V0:.+]] = vector.extract %[[TRANSPOSED]][0] : vector<4x2xf32>
13 // CHECK: %[[V1:.+]] = vector.extract %[[TRANSPOSED]][1] : vector<4x2xf32>
15 // CHECK: %[[V2:.+]] = vector.extract %[[TRANSPOSED]][2] : vector<4x2xf32>
17 // CHECK: %[[V3:.+]] = vector.extract %[[TRANSPOSED]][3] : vector<4x2xf32>
29 // CHECK: %[[V0:.+]] = vector.extract %[[TRANSPOSED]][0] : vector<4x2xf32>
31 // CHECK: %[[V1:.+]] = vector.extract %[[TRANSPOSED]][1] : vector<4x2xf32>
33 // CHECK: %[[V2:.+]] = vector.extract %[[TRANSPOSED]][2] : vector<4x2xf32>
35 // CHECK: %[[V3:.+]] = vector.extract %[[TRANSPOSED]][3] : vector<4x2xf32>
47 // CHECK: %[[V0:.+]] = vector.extract %[[TRANSPOSED]][0] : vector<4x2xf32>
49 // CHECK: %[[V1:.+]] = vector.extract %[[TRANSPOSED]][1] : vector<4x2xf32>
[all …]
H A Dvector-multi-reduction-lowering.mlir12 // CHECK: %[[V0:.+]] = vector.extract %[[INPUT]][0]
13 // CHECK: %[[ACC0:.+]] = vector.extract %[[ACC]][0]
16 // CHECK: %[[V1:.+]] = vector.extract %[[INPUT]][1]
17 // CHECK: %[[ACC1:.+]] = vector.extract %[[ACC]][1]
31 // CHECK: %[[RES:.*]] = vector.extract %[[INSERTED]][0] : vector<1xf32>
104 // CHECK: %[[V0:.+]] = vector.extract %[[TRANSPOSED_INPUT]][0, 0]
108 // CHECK: %[[V1:.+]] = vector.extract %[[TRANSPOSED_INPUT]][0, 1]
112 // CHECK: %[[V2:.+]] = vector.extract %[[TRANSPOSED_INPUT]][0, 2]
116 // CHECK: %[[V3:.+]] = vector.extract %[[TRANSPOSED_INPUT]][0, 3]
120 // CHECK: %[[V4:.+]] = vector.extract %[[TRANSPOSED_INPUT]][1, 0]
[all …]
H A Dvector-transpose-lowering.mlir51 // AVX2: vector.extract {{.*}}[0]
52 // AVX2-NEXT: vector.extract {{.*}}[1]
53 // AVX2-NEXT: vector.extract {{.*}}[2]
54 // AVX2-NEXT: vector.extract {{.*}}[3]
111 // AVX2: vector.extract {{.*}}[0]
112 // AVX2-NEXT: vector.extract {{.*}}[1]
113 // AVX2-NEXT: vector.extract {{.*}}[2]
114 // AVX2-NEXT: vector.extract {{.*}}[3]
115 // AVX2-NEXT: vector.extract {{.*}}[4]
116 // AVX2-NEXT: vector.extract {{.*}}[5]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/EarlyCSE/AArch64/
H A Dintrinsics.ll22 %0 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
23 %1 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
30 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)
43 …vm.aarch64.neon.st2.v4i32.p0(<4 x i32> %s.coerce.fca.0.extract, <4 x i32> %s.coerce.fca.1.extract,…
55 %0 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8>
56 %1 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8>
64 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)
95 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld22.fca.0.extract)
130 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)
163 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.2.extract)
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dcanonicalize-vector-extract.ll4 ; llvm.vector.extract canonicalizes to shufflevector in the fixed case. In the
7 declare <10 x i32> @llvm.vector.extract.v10i32.v8i32(<8 x i32> %vec, i64 %idx)
8 declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 %idx)
9 declare <3 x i32> @llvm.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 %idx)
11 declare <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 %idx)
12 declare <8 x i32> @llvm.vector.extract.v8i32.v8i32(<8 x i32> %vec, i64 %idx)
23 %1 = call <8 x i32> @llvm.vector.extract.v8i32.v8i32(<8 x i32> %vec, i64 0)
36 %1 = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 0)
45 %1 = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 2)
54 %1 = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 4)
[all …]
/llvm-project-15.0.7/llvm/docs/CommandGuide/
H A Dllvm-extract.rst1 llvm-extract - extract a function from an LLVM module
4 .. program:: llvm-extract
9 :program:`llvm-extract` [*options*] **--func** *function-name* [*filename*]
14 The :program:`llvm-extract` command takes the name of a function and extracts
19 :program:`llvm-extract` will also remove unreachable global variables,
22 The :program:`llvm-extract` command reads its input from standard input if
32 specified multiple times to extract multiple alias at once.
61 specified multiple times to extract multiple functions at once.
72 specified multiple times to extract multiple global variables at once.
86 Recursively extract all called functions
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/BlockExtractor/
H A Dextract-blocks.ll3 ; RUN: opt -S -extract-blocks -extract-blocks-file=%t %s | FileCheck %s --check-prefix=CHECK-NO-ERA…
4 ; RUN: opt -S -extract-blocks -extract-blocks-file=%t -extract-blocks-erase-funcs %s | FileCheck %s…
5 ; RUN: opt -S -passes=extract-blocks -extract-blocks-file=%t %s | FileCheck %s --check-prefix=CHECK…
6 ; RUN: opt -S -passes=extract-blocks -extract-blocks-file=%t -extract-blocks-erase-funcs %s | FileC…
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dparam-vectorize-device.ll98 store i32 %.fca.0.extract, ptr %ret, align 4
133 store i32 %.fca.0.extract, ptr %ret, align 4
174 store i32 %.fca.0.extract, ptr %ret, align 4
221 store i32 %.fca.0.extract, ptr %ret, align 4
274 store i32 %.fca.0.extract, ptr %ret, align 4
335 store i32 %.fca.0.extract, ptr %ret, align 4
404 store i32 %.fca.0.extract, ptr %ret, align 4
479 store i32 %.fca.0.extract, ptr %ret, align 4
549 store i64 %.fca.0.extract, ptr %ret, align 8
581 store i64 %.fca.0.extract, ptr %ret, align 8
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Drv64i-complex-float.ll34 %a.sroa.0.0.extract.trunc = trunc i64 %a.coerce to i32
35 %0 = bitcast i32 %a.sroa.0.0.extract.trunc to float
36 %a.sroa.2.0.extract.shift = lshr i64 %a.coerce, 32
37 %a.sroa.2.0.extract.trunc = trunc i64 %a.sroa.2.0.extract.shift to i32
38 %1 = bitcast i32 %a.sroa.2.0.extract.trunc to float
39 %b.sroa.0.0.extract.trunc = trunc i64 %b.coerce to i32
40 %2 = bitcast i32 %b.sroa.0.0.extract.trunc to float
41 %b.sroa.2.0.extract.shift = lshr i64 %b.coerce, 32
42 %b.sroa.2.0.extract.trunc = trunc i64 %b.sroa.2.0.extract.shift to i32
43 %3 = bitcast i32 %b.sroa.2.0.extract.trunc to float
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dextract-subvector.ll10 %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)
378 %c = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1(<vscale x 64 x i1> %mask, i64 0)
390 %c = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1(<vscale x 64 x i1> %mask, i64 8)
398 %c = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1(<vscale x 64 x i1> %mask, i64 0)
415 %c = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1(<vscale x 64 x i1> %mask, i64 2)
423 %c = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1(<vscale x 32 x i1> %x, i64 0)
440 %c = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1(<vscale x 32 x i1> %x, i64 4)
448 %c = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1(<vscale x 32 x i1> %x, i64 0)
514 declare <vscale x 4 x i1> @llvm.vector.extract.nxv4i1(<vscale x 32 x i1> %vec, i64 %idx)
517 declare <vscale x 2 x i1> @llvm.vector.extract.nxv2i1(<vscale x 64 x i1> %vec, i64 %idx)
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