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/llvm-project-15.0.7/llvm/test/Transforms/LoopUnrollAndJam/
H A Dunroll-and-jam-many-instr.ll37 %lor.ext = zext i1 %tobool21 to i32
38 %xor = xor i32 %i.addr.041, %lor.ext
40 %lor.ext.1 = zext i1 %tobool21.1 to i32
41 %xor.1 = xor i32 %xor, %lor.ext.1
44 %xor.2 = xor i32 %xor.1, %lor.ext.2
47 %xor.3 = xor i32 %xor.2, %lor.ext.3
50 %xor.4 = xor i32 %xor.3, %lor.ext.4
53 %xor.5 = xor i32 %xor.4, %lor.ext.5
56 %xor.6 = xor i32 %xor.5, %lor.ext.6
59 %xor.7 = xor i32 %xor.6, %lor.ext.7
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/ScalarEvolution/
H A Davoid-assume-hang.ll9 %cmp0 = icmp ne i64 %i.ext, %a
13 %cmp1 = icmp ne i64 %i.ext, %a1
17 %cmp2 = icmp ne i64 %i.ext, %a2
21 %cmp3 = icmp ne i64 %i.ext, %a3
25 %cmp4 = icmp ne i64 %i.ext, %a4
35 %cmp1 = icmp ne i64 %i.ext, %a1
39 %cmp2 = icmp ne i64 %i.ext, %a2
43 %cmp3 = icmp ne i64 %i.ext, %a3
47 %cmp4 = icmp ne i64 %i.ext, %a4
127 %i.ext = zext i32 %i to i64
[all …]
H A Dnon-IV-phi.ll5 ; CHECK: %sphi = phi i32 [ %ext, %entry ], [ %idx.inc.ext, %loop ]
10 %ext = zext i8 %t to i32
17 %sphi = phi i32 [ %ext, %entry ], [%idx.inc.ext, %loop]
20 %idx.inc.ext = zext i8 %idx.inc to i32
21 %idx.ext = zext i8 %idx to i32
23 %c = icmp ult i32 %idx.inc.ext, %len
37 %ext = zext i8 %t to i32
38 %ext.mul = mul i32 %ext, 4
50 %mul = mul i32 %idx.inc.ext, 4
52 %idx.ext = zext i8 %idx to i32
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmad-mix.ll15 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
36 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
52 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
112 %src0.ext.neg = fneg float %src0.ext
113 %result = tail call float @llvm.fmuladd.f32(float %src0.ext.neg, float %src1.ext, float %src2.ext)
146 %src0.ext.neg.abs = fneg float %src0.ext.abs
407 %mul = fmul float %src0.ext, %src1.ext
420 %mul = fmul float %src0.ext, %src1.ext
434 %mul = fmul contract float %src0.ext, %src1.ext
447 %mul = fmul contract float %src0.ext, %src1.ext
[all …]
H A Dmad-mix-hi.ll13 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
29 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
44 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
60 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
63 %ext = zext i16 %bc to i32
64 %shr = shl i32 %ext, 16
77 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
81 %shr = shl i32 %ext, 16
94 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
110 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
[all …]
H A Dglobal-extload-i16.ll12 %ext = zext i16 %a to i32
13 store i32 %ext, i32 addrspace(1)* %out
23 %ext = sext i16 %a to i32
24 store i32 %ext, i32 addrspace(1)* %out
33 %ext = zext <1 x i16> %load to <1 x i32>
43 %ext = sext <1 x i16> %load to <1 x i32>
52 %ext = zext <2 x i16> %load to <2 x i32>
61 %ext = sext <2 x i16> %load to <2 x i32>
162 %ext = zext i16 %a to i64
163 store i64 %ext, i64 addrspace(1)* %out
[all …]
H A Dload-constant-i1.ll72 %ext = zext i1 %a to i32
73 store i32 %ext, i32 addrspace(1)* %out
86 %ext = sext i1 %a to i32
87 store i32 %ext, i32 addrspace(1)* %out
94 %ext = zext <1 x i1> %load to <1 x i32>
102 %ext = sext <1 x i1> %load to <1 x i32>
110 %ext = zext <2 x i1> %load to <2 x i32>
118 %ext = sext <2 x i1> %load to <2 x i32>
126 %ext = zext <3 x i1> %load to <3 x i32>
226 %ext = zext i1 %a to i64
[all …]
H A Dload-global-i1.ll72 %ext = zext i1 %a to i32
73 store i32 %ext, i32 addrspace(1)* %out
86 %ext = sext i1 %a to i32
87 store i32 %ext, i32 addrspace(1)* %out
94 %ext = zext <1 x i1> %load to <1 x i32>
102 %ext = sext <1 x i1> %load to <1 x i32>
110 %ext = zext <2 x i1> %load to <2 x i32>
118 %ext = sext <2 x i1> %load to <2 x i32>
126 %ext = zext <3 x i1> %load to <3 x i32>
226 %ext = zext i1 %a to i64
[all …]
H A Dmad-mix-lo.ll29 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
101 …l <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> %src2.…
122 …l <3 x float> @llvm.fmuladd.v3f32(<3 x float> %src0.ext, <3 x float> %src1.ext, <3 x float> %src2.…
146 …l <4 x float> @llvm.fmuladd.v4f32(<4 x float> %src0.ext, <4 x float> %src1.ext, <4 x float> %src2.…
165 …l <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> %src2.…
191 …l <3 x float> @llvm.fmuladd.v3f32(<3 x float> %src0.ext, <3 x float> %src1.ext, <3 x float> %src2.…
219 …l <4 x float> @llvm.fmuladd.v4f32(<4 x float> %src0.ext, <4 x float> %src1.ext, <4 x float> %src2.…
240 …l <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> %src2.…
263 …l <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> %src2.…
288 …l <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> %src2.…
[all …]
H A Dload-local-i1.ll94 %ext = zext i1 %a to i32
95 store i32 %ext, i32 addrspace(3)* %out
111 %ext = sext i1 %a to i32
112 store i32 %ext, i32 addrspace(3)* %out
121 %ext = zext <1 x i1> %load to <1 x i32>
131 %ext = sext <1 x i1> %load to <1 x i32>
141 %ext = zext <2 x i1> %load to <2 x i32>
151 %ext = sext <2 x i1> %load to <2 x i32>
161 %ext = zext <3 x i1> %load to <3 x i32>
285 %ext = zext i1 %a to i64
[all …]
H A Dicmp.i16.ll14 %tid.ext = sext i32 %tid to i64
32 %tid.ext = sext i32 %tid to i64
50 %tid.ext = sext i32 %tid to i64
68 %tid.ext = sext i32 %tid to i64
86 %tid.ext = sext i32 %tid to i64
104 %tid.ext = sext i32 %tid to i64
123 %tid.ext = sext i32 %tid to i64
141 %tid.ext = sext i32 %tid to i64
159 %tid.ext = sext i32 %tid to i64
177 %tid.ext = sext i32 %tid to i64
[all …]
H A Dsetcc-opt.ll17 %ext = sext i1 %icmp0 to i32
18 %icmp1 = icmp eq i32 %ext, 0
35 %ext = sext i1 %icmp0 to i32
36 %icmp1 = icmp ne i32 %ext, 0
50 %ext = sext i1 %icmp0 to i32
65 %ext = sext i1 %icmp0 to i32
173 %b.ext = zext i8 %b to i32
187 %b.ext = sext i8 %b to i32
198 %b.ext = sext i8 %b to i32
218 %b.ext = sext i8 %b to i32
[all …]
H A Dcommute-compares.ll17 %ext = sext i1 %cmp to i32
30 %ext = sext i1 %cmp to i32
45 %ext = sext i1 %cmp to i32
58 %ext = sext i1 %cmp to i32
71 %ext = sext i1 %cmp to i32
84 %ext = sext i1 %cmp to i32
97 %ext = sext i1 %cmp to i32
111 %ext = sext i1 %cmp to i32
124 %ext = sext i1 %cmp to i32
137 %ext = sext i1 %cmp to i32
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dfloat-shrink-compare.ll12 %x.ext = fpext float %x to double
14 %ext.y = fpext float %y to double
15 %cmp = fcmp oeq double %ceil, %ext.y
25 %x.ext = fpext float %x to double
27 %ext.y = fpext float %y to double
38 %x.ext = fpext float %x to double
40 %y.ext = fpext float %y to double
51 %x.ext = fpext float %x to double
53 %y.ext = fpext float %y to double
77 %x.ext = fpext float %x to double
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/SVE2/
H A Dext-diagnostics.s7 ext z0.h, { z1.h, z2.h }, #0 label
12 ext z0.s, { z1.s, z2.s }, #0 label
17 ext z0.d, { z1.d, z2.d }, #0 label
26 ext z0.b, { z1.b, z2.b }, #-1 label
31 ext z0.b, { z1.b, z2.b }, #256 label
40 ext z0.b, { }, #0 label
45 ext z0.b, { z1.b }, #0 label
50 ext z0.b, { z1.b, z2.b, z3.b }, #0 label
55 ext z0.b, { z1.b, z2.h }, #0 label
60 ext z0.b, { z1.b, z31.b }, #0 label
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/ConstraintElimination/
H A Dzext.ll30 %x.ext = zext i8 %x to i16
83 %x.ext = zext i8 %x to i16
84 %y.ext = zext i8 %y to i16
88 %t.1 = icmp uge i16 %x.ext, %y.ext
91 %c.3 = icmp sge i16 %y.ext, %x.ext
98 %t.2 = icmp uge i16 %y.ext, %x.ext
99 %f.1 = icmp uge i16 %x.ext, %y.ext
248 %t.1 = icmp sge i16 %x.ext, %y.ext
251 %c.3 = icmp sge i16 %y.ext, %x.ext
258 %t.2 = icmp sge i16 %y.ext, %x.ext
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmax-jump-table.ll7 declare void @ext(i32, i32)
47 bb1: tail call void @ext(i32 1, i32 0) br label %return
48 bb2: tail call void @ext(i32 2, i32 2) br label %return
49 bb3: tail call void @ext(i32 3, i32 4) br label %return
50 bb4: tail call void @ext(i32 4, i32 6) br label %return
93 bb1: tail call void @ext(i32 6, i32 1) br label %return
94 bb2: tail call void @ext(i32 5, i32 2) br label %return
95 bb3: tail call void @ext(i32 4, i32 3) br label %return
96 bb4: tail call void @ext(i32 3, i32 4) br label %return
97 bb5: tail call void @ext(i32 2, i32 5) br label %return
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Druntime-check-size-based-threshold.ll21 %ext.1 = sext i16 %lv.1 to i32
24 %ext.2 = sext i16 %lv.2 to i32
27 %ext.3 = sext i16 %lv.3 to i32
30 %ext.4 = sext i16 %lv.4 to i32
31 %tmp62 = mul nsw i32 %ext.2, 11
32 %tmp66 = mul nsw i32 %ext.3, -4
39 %tmp76 = mul nsw i32 %ext.2, 5
40 %tmp77 = shl nsw i32 %ext.3, 2
76 %ext.1 = sext i16 %lv.1 to i32
79 %ext.2 = sext i16 %lv.2 to i32
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dint-conv-12.ll10 %ext = and i64 %a, 2147483647
11 ret i64 %ext
20 %ext = zext i32 %and to i64
21 ret i64 %ext
29 %ext = zext i32 %a to i64
40 %ext = zext i32 %word to i64
52 %ext = zext i32 %and to i64
53 ret i64 %ext
63 %ext = zext i32 %word to i64
77 %ext = zext i32 %word to i64
[all …]
H A Dint-conv-10.ll10 %ext = zext i32 %a to i64
11 ret i64 %ext
21 ret i64 %ext
30 ret i64 %ext
40 ret i64 %ext
51 ret i64 %ext
64 ret i64 %ext
75 ret i64 %ext
86 ret i64 %ext
99 ret i64 %ext
[all …]
H A Dint-conv-09.ll10 %ext = sext i32 %a to i64
11 ret i64 %ext
20 %ext = sext i32 %word to i64
21 ret i64 %ext
31 ret i64 %ext
42 ret i64 %ext
55 ret i64 %ext
66 ret i64 %ext
77 ret i64 %ext
90 ret i64 %ext
[all …]
H A Dfp-move-08.ll12 %ext = fpext double %val to fp128
13 store fp128 %ext, fp128 *%ptr
25 %ext = fpext double %val to fp128
26 store fp128 %ext, fp128 *%ptr
39 store fp128 %ext, fp128 *%ptr
52 store fp128 %ext, fp128 *%ptr
65 store fp128 %ext, fp128 *%ptr
80 store fp128 %ext, fp128 *%ptr
94 store fp128 %ext, fp128 *%ptr
107 store fp128 %ext, fp128 *%ptr
[all …]
H A Dint-cmp-21.ll14 %ext = zext i8 %val to i64
15 %cond = icmp ugt i64 %ext, 1
28 %ext = sext i8 %val to i64
29 %cond = icmp ugt i64 %ext, 1
42 %ext = zext i8 %val to i64
56 %ext = sext i8 %val to i64
69 %ext = zext i8 %val to i64
85 %ext = sext i8 %val to i64
97 %ext = sext i8 %val to i64
111 %ext = zext i8 %val to i64
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SCCP/
H A Dip-ranges-sext.ll20 ret i64 %ext.1
24 ret i64 %ext.2
43 ret i64 %ext.1
47 ret i64 %ext.2
67 ret i64 %ext.1
71 ret i64 %ext.2
102 ret i64 %ext
113 ret i64 %ext
122 ret i64 %ext
135 %ext.2 = sext i32 %ext.1 to i64
[all …]
/llvm-project-15.0.7/llvm/test/MC/M68k/Arith/Classes/
H A DMxExt.s3 ; CHECK: ext.w %d0
5 ext.w %d0
6 ; CHECK: ext.w %d3
8 ext.w %d3
9 ; CHECK: ext.l %d0
11 ext.l %d0
12 ; CHECK: ext.l %d7
14 ext.l %d7

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