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Searched refs:enablePostRAScheduler (Results 1 – 11 of 11) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetSubtargetInfo.cpp48 bool TargetSubtargetInfo::enablePostRAScheduler() const { in enablePostRAScheduler() function in TargetSubtargetInfo
53 return enableMachineScheduler() && enablePostRAScheduler(); in enablePostRAMachineScheduler()
H A DPostRASchedulerList.cpp103 bool enablePostRAScheduler(
262 bool PostRAScheduler::enablePostRAScheduler( in enablePostRAScheduler() function in PostRAScheduler
274 return ST.enablePostRAScheduler() && in enablePostRAScheduler()
295 if (!enablePostRAScheduler(Fn.getSubtarget(), PassConfig->getOptLevel(), in runOnMachineFunction()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetSubtargetInfo.h209 virtual bool enablePostRAScheduler() const;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCSubtarget.cpp212 bool PPCSubtarget::enablePostRAScheduler() const { return true; } in enablePostRAScheduler() function in PPCSubtarget
H A DPPCSubtarget.h386 bool enablePostRAScheduler() const override;
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSubtarget.h229 bool enablePostRAScheduler() const override;
H A DMipsSubtarget.cpp230 bool MipsSubtarget::enablePostRAScheduler() const { return true; } in enablePostRAScheduler() function in MipsSubtarget
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64Subtarget.h182 bool enablePostRAScheduler() const override { return usePostRAScheduler(); } in enablePostRAScheduler() function
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.h268 bool enablePostRAScheduler() const override { return true; } in enablePostRAScheduler() function
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSubtarget.h477 bool enablePostRAScheduler() const override;
H A DARMSubtarget.cpp405 bool ARMSubtarget::enablePostRAScheduler() const { in enablePostRAScheduler() function in ARMSubtarget