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/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dfixed-vectors-extract-subvector.ll8 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
10 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
22 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
24 ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
26 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
38 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
40 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
52 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
54 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
56 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
[all …]
H A Dfixed-vectors-insert-i1.ll11 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
22 ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
27 ; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
29 ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
36 ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
42 ; RV64-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
44 ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
55 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
72 ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
77 ; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
[all …]
H A Dinsertelt-i1.ll8 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
12 ; CHECK-NEXT: vsetivli zero, 3, e8, mf8, tu, mu
14 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
25 ; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
30 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
32 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
43 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
47 ; CHECK-NEXT: vsetivli zero, 3, e8, mf4, tu, mu
49 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
60 ; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu
[all …]
H A Dfixed-vectors-mask-splat.ll10 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
14 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
16 ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu
18 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
29 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
33 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
35 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
37 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
49 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
54 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
[all …]
H A Dfixed-vectors-mask-load-store.ll10 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
14 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
16 ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu
18 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
30 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
34 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
36 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
38 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
50 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
54 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
[all …]
H A Dfixed-vectors-vreductions-mask.ll12 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
28 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
44 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
60 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
76 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
92 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
108 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
124 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
138 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
152 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
[all …]
H A Dextractelt-i1.ll8 ; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
13 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
26 ; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu
31 ; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
44 ; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
49 ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
63 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
67 ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
81 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
85 ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu
[all …]
H A Dfixed-vectors-setcc-int-vp-mask.ll13 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
25 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
37 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
49 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
59 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
69 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
79 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
89 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
99 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
129 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
[all …]
H A Dvreductions-mask.ll10 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
24 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
38 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
53 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
67 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
82 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
97 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
111 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
125 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
139 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
[all …]
H A Dvsplats-i1.ll8 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
19 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
31 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
45 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
58 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
69 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
81 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
93 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
128 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
139 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
[all …]
H A Dvmarith-sdnode.ll8 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
18 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
28 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
38 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
48 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
58 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
68 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
78 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
88 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
98 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
[all …]
H A Dfixed-vectors-int-exttrunc.ll56 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
58 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
86 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
88 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, m1, ta, mu
92 ; LMULMAX2-NEXT: vsetivli zero, 16, e8, m2, ta, mu
94 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, m1, ta, mu
111 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
115 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
119 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu
129 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu
[all …]
H A Dfixed-vectors-select-int.ll10 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
26 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
41 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
57 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
72 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
88 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
103 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
119 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
134 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
150 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
[all …]
H A Dsetcc-int-vp-mask.ll12 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
24 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
36 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
48 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
60 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
72 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
84 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
124 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
134 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
144 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
[all …]
H A Dfixed-vectors-fp2i.ll150 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
157 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
160 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
184 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
194 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
344 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
356 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
373 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
391 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
459 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
[all …]
H A Dfixed-vectors-fp-setcc.ll44 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
47 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
49 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
51 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
72 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
74 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
76 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
97 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
99 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
101 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
[all …]
H A Dfixed-vectors-extract-i1.ll11 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
28 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
33 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
46 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
51 ; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
64 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
74 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
108 ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
119 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
157 ; RV32-NEXT: vsetvli zero, a2, e8, m2, ta, mu
[all …]
H A Dfixed-vectors-select-fp.ll10 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
24 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
38 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
52 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
66 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
80 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
94 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
108 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
122 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
136 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
[all …]
H A Dfixed-vectors-marith-vp.ll12 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
24 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
36 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
48 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
60 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
72 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
84 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
96 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
108 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
120 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
[all …]
H A Dselect-fp.ll10 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
24 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
38 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
52 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
66 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
80 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
94 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
108 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
122 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
136 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
[all …]
H A Dfixed-vectors-int-shuffles.ll9 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
22 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
35 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
48 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
106 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
246 ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
281 ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
415 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
429 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
464 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
[all …]
H A Dselect-int.ll10 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
26 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
41 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
57 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
72 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
88 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
103 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
119 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
134 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
150 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
[all …]
H A Dvrgatherei16-subreg-liveness.ll18 ; NOSUBREG-NEXT: vsetvli zero, zero, e8, m1, ta, mu
20 ; NOSUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, mu
26 ; NOSUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, mu
29 ; NOSUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, mu
38 ; SUBREG-NEXT: vsetvli zero, zero, e8, m1, ta, mu
40 ; SUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, mu
46 ; SUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, mu
49 ; SUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, mu
/llvm-project-15.0.7/llvm/test/Object/X86/
H A Dobjdump-trivial-object.test9 # COFF-i386: 12: e8 00 00 00 00 calll 0
10 # COFF-i386: 17: e8 00 00 00 00 calll 0
23 # COFF-x86-64: 13: e8 00 00 00 00 callq 0
24 # COFF-x86-64: 18: e8 00 00 00 00 callq 0
37 # ELF-i386: 12: e8 fc ff ff ff calll 0x13
38 # ELF-i386: 17: e8 fc ff ff ff calll 0x18
63 # ELF-x86-64: 11: e8 00 00 00 00 callq 0
65 # ELF-x86-64: 18: e8 00 00 00 00 callq 0
H A Dobjdump-disassembly-inline-relocations.test10 # COFF-i386: 12: e8 00 00 00 00 calll 0
12 # COFF-i386: 17: e8 00 00 00 00 calll 0
27 # COFF-x86-64: 13: e8 00 00 00 00 callq 0
29 # COFF-x86-64: 18: e8 00 00 00 00 callq 0
45 # MACHO-i386: 12: e8 1f 00 00 00 calll 0x36
63 # MACHO-x86-64: 13: e8 00 00 00 00 callq 0
66 # MACHO-x86-64: 1a: e8 00 00 00 00 callq 0
82 # ELF-i386: 12: e8 fc ff ff ff calll 0x13
84 # ELF-i386: 17: e8 fc ff ff ff calll 0x18
180 # ELF-x86-64: 11: e8 00 00 00 00 callq 0
[all …]

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