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Searched refs:ds_read2_b32 (Results 1 – 25 of 42) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlds-misaligned-bug.ll8 ; GCN-DAG: ds_read2_b32
25 ; ALIGNED-DAG: ds_read2_b32
26 ; ALIGNED-DAG: ds_read2_b32
50 ; ALIGNED-DAG: ds_read2_b32
109 ; ALIGNED-WGP-DAG: ds_read2_b32
110 ; ALIGNED-WGP-DAG: ds_read2_b32
H A Dload-local.128.ll351 ; GFX9-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
352 ; GFX9-NEXT: ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
361 ; GFX7-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
362 ; GFX7-NEXT: ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
371 ; GFX10-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
372 ; GFX10-NEXT: ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
410 ; GFX10-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
411 ; GFX10-NEXT: ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
H A Dload-local.96.ll292 ; GFX9-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
302 ; GFX7-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
312 ; GFX10-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
335 ; GFX9-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
345 ; GFX7-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
355 ; GFX10-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
H A Dload-unaligned.ll80 ; GFX10-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
81 ; GFX10-NEXT: ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
153 ; GFX10-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dds_read2.ll17 ; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:8
30 ; GFX9-NEXT: ds_read2_b32 v[0:1], v2 offset1:8
53 ; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:255
66 ; GFX9-NEXT: ds_read2_b32 v[0:1], v2 offset1:255
127 ; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:8
143 ; GFX9-NEXT: ds_read2_b32 v[0:1], v4 offset1:8
183 ; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:8
201 ; GFX9-NEXT: ds_read2_b32 v[0:1], v4 offset1:8
412 ; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:8
906 ; CI-NEXT: ds_read2_b32 v[1:2], v3 offset1:1
[all …]
H A Dds_read2_superreg.ll11 ; CI: ds_read2_b32 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
39 ; CI-DAG: ds_read2_b32 v[[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}
40 ; CI-DAG: ds_read2_b32 v[[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}
65 ; CI-DAG: ds_read2_b32 v[[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}
152 ; CI-DAG: ds_read2_b32 v[[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}
174 ; CI-DAG: ds_read2_b32 v[[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}
175 ; CI-DAG: ds_read2_b32 v[[[REG_ELT2:[0-9]+]]:[[REG_ELT3:[0-9]+]]], v{{[0-9]+}} offset0:2 offset1:3{…
H A Dds-combine-large-stride.ll16 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100
17 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:72 offset1:172
18 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset0:144 offset1:244
19 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset0:88 offset1:188
59 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:144 offset1:164
60 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:184 offset1:204
61 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:224 offset1:244
62 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset0:8 offset1:28
105 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100
106 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:88 offset1:188
[all …]
H A Dds_read2_offset_order.ll11 ; SI-DAG: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:11 offset1:12
12 ; SI-DAG: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:6 offset1:248
H A Dlds-bounds.ll48 ; GCN: ds_read2_b32
82 ; NOSI: ds_read2_b32
113 ; GCN: ds_read2_b32
H A Dds-negative-offset-addressing-mode-loop.ll22 ; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset1:2
23 ; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:32 offset1:34
H A Dllvm.memcpy.ll136 ; SI: ds_read2_b32
137 ; SI: ds_read2_b32
138 ; SI: ds_read2_b32
139 ; SI: ds_read2_b32
H A Dsi-triv-disjoint-mem-access.ll9 ; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:1 offset1:3
12 ; GFX9: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:1 offset1:3
186 ; GCN: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:100 offset1:102
294 ; GCN: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:1 offset1:2
H A Dlds-misaligned-bug.ll8 ; GCN-DAG: ds_read2_b32
25 ; GCN-DAG: ds_read2_b32
26 ; GCN-DAG: ds_read2_b32
48 ; GCN-DAG: ds_read2_b32
H A Dds-combine-with-dependence.ll10 ; GCN-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:8
42 ; GCN: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:27
H A Dload-local.128.ll449 ; GFX9-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
450 ; GFX9-NEXT: ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
459 ; GFX7-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
460 ; GFX7-NEXT: ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
483 ; GFX10-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
484 ; GFX10-NEXT: ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
H A Dlocal-memory.ll32 ; GCN-DAG: ds_read2_b32
H A Dds-alignment.ll353 ; GCN-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
561 ; ALIGNED-NEXT: ds_read2_b32 v[0:1], v2 offset1:1
575 ; UNALIGNED-SDAG-NEXT: ds_read2_b32 v[0:1], v2 offset1:1
619 ; ALIGNED-GISEL-NEXT: ds_read2_b32 v[0:1], v2 offset1:1
893 ; ALIGNED-NEXT: ds_read2_b32 v[0:1], v2 offset1:1
894 ; ALIGNED-NEXT: ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
907 ; UNALIGNED-SDAG-NEXT: ds_read2_b32 v[0:1], v2 offset0:2 offset1:3
908 ; UNALIGNED-SDAG-NEXT: ds_read2_b32 v[2:3], v2 offset1:1
H A Dunaligned-load-store.ll340 ; GCN: ds_read2_b32
348 ; GCN: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset0:8 offset1:9
358 ; GCN: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset1:1
/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dds.s50 ds_read2_b32 v[8:9], v2 offset0:4 label
54 ds_read2_b32 v[8:9], v2 offset0:4 offset1:8 label
58 ds_read2_b32 v[8:9], v2 offset1:8 label
282 ds_read2_b32 v[8:9], v2 label
H A Delf-lds.s10 ds_read2_b32 v[1:2], v3 offset1:1
H A Dgfx7_asm_ds.s1164 ds_read2_b32 v[5:6], v1 offset0:127 offset1:255 label
1167 ds_read2_b32 v[254:255], v1 offset0:127 offset1:255 label
1170 ds_read2_b32 v[5:6], v255 offset0:127 offset1:255 label
1173 ds_read2_b32 v[5:6], v1 offset1:255 label
1176 ds_read2_b32 v[5:6], v1 offset0:0 offset1:255 label
1179 ds_read2_b32 v[5:6], v1 offset0:16 offset1:255 label
1182 ds_read2_b32 v[5:6], v1 offset0:127 label
1185 ds_read2_b32 v[5:6], v1 offset0:127 offset1:0 label
1188 ds_read2_b32 v[5:6], v1 offset0:127 offset1:1 label
1191 ds_read2_b32 v[5:6], v1 offset0:127 offset1:255 gds label
H A Dgfx11_ds.s30 ds_read2_b32 v[254:255], v1 offset0:127 offset1:255 label
H A Dgfx8_asm_ds.s1107 ds_read2_b32 v[5:6], v1 offset0:127 offset1:255 label
1110 ds_read2_b32 v[254:255], v1 offset0:127 offset1:255 label
1113 ds_read2_b32 v[5:6], v255 offset0:127 offset1:255 label
1116 ds_read2_b32 v[5:6], v1 offset1:255 label
1119 ds_read2_b32 v[5:6], v1 offset0:0 offset1:255 label
1122 ds_read2_b32 v[5:6], v1 offset0:16 offset1:255 label
1125 ds_read2_b32 v[5:6], v1 offset0:127 label
1128 ds_read2_b32 v[5:6], v1 offset0:127 offset1:0 label
1131 ds_read2_b32 v[5:6], v1 offset0:127 offset1:1 label
1134 ds_read2_b32 v[5:6], v1 offset0:127 offset1:255 gds label
H A Dgfx9_asm_ds.s1125 ds_read2_b32 v[5:6], v1 offset0:127 offset1:255 label
1128 ds_read2_b32 v[254:255], v1 offset0:127 offset1:255 label
1131 ds_read2_b32 v[5:6], v255 offset0:127 offset1:255 label
1134 ds_read2_b32 v[5:6], v1 offset1:255 label
1137 ds_read2_b32 v[5:6], v1 offset0:0 offset1:255 label
1140 ds_read2_b32 v[5:6], v1 offset0:16 offset1:255 label
1143 ds_read2_b32 v[5:6], v1 offset0:127 label
1146 ds_read2_b32 v[5:6], v1 offset0:127 offset1:0 label
1149 ds_read2_b32 v[5:6], v1 offset0:127 offset1:1 label
1152 ds_read2_b32 v[5:6], v1 offset0:127 offset1:255 gds label
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/
H A Dds_vi.txt15 # VI: ds_read2_b32 v[8:9], v2 offset0:4 ; encoding: [0x04,0x00,0x6e,0xd8,0x02,0x00,0x00,0x08]
18 # VI: ds_read2_b32 v[8:9], v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x6e,0xd8,0x02,0x00,0x00…
21 # VI: ds_read2_b32 v[8:9], v2 offset1:8 ; encoding: [0x00,0x08,0x6e,0xd8,0x02,0x00,0x00,0x08]
180 # VI: ds_read2_b32 v[8:9], v2 ; encoding: [0x00,0x00,0x6e,0xd8,0x02,0x00,0x00,0x08]

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