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/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Ddirective-arch_extension-idiv.s27 @ CHECK-ARMv6: error: instruction requires: divide in ARM
28 @ CHECK-THUMBv6: error: instruction requires: divide in THUMB armv8m.base
30 @ CHECK-ARMv6: error: instruction requires: divide in ARM
31 @ CHECK-THUMBv6: error: instruction requires: divide in THUMB armv8m.base
44 @ CHECK-ARMv6: error: instruction requires: divide in ARM
45 @ CHECK-THUMBv6: error: instruction requires: divide in THUMB armv8m.base
46 @ CHECK-ARMv7: error: instruction requires: divide in ARM
47 @ CHECK-THUMBv7: error: instruction requires: divide in THUMB
49 @ CHECK-ARMv6: error: instruction requires: divide in ARM
51 @ CHECK-ARMv7: error: instruction requires: divide in ARM
[all …]
H A Dinvalid-idiv.s12 @ ARM-A15: note: instruction requires: divide in ARM
15 @ ARM-A15: note: instruction requires: divide in ARM
19 @ THUMB-A15: note: instruction requires: divide in THUMB
22 @ THUMB-A15: note: instruction requires: divide in THUMB
25 @ ARM: error: instruction requires: divide in ARM
27 @ ARM: error: instruction requires: divide in ARM
29 @ THUMB: error: instruction requires: divide in THUMB
31 @ THUMB: error: instruction requires: divide in THUMB
H A Ddirective-arch_extension-mode-switch.s12 @ CHECK: instruction requires: divide in ARM
16 @ CHECK: instruction requires: divide in THUMB
/llvm-project-15.0.7/libclc/generic/lib/math/
H A Dhalf_divide.cl3 #define divide(x,y) (x/y)
5 #define __CLC_FUNC divide
9 #undef divide
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DScalarEvolutionDivision.cpp55 void SCEVDivision::divide(ScalarEvolution &SE, const SCEV *Numerator, in divide() function in SCEVDivision
88 divide(SE, *Quotient, Op, &Q, &R); in divide()
133 divide(SE, Numerator->getStart(), Denominator, &StartQ, &StartR); in visitAddRecExpr()
134 divide(SE, Numerator->getStepRecurrence(SE), Denominator, &StepQ, &StepR); in visitAddRecExpr()
152 divide(SE, Op, Denominator, &Q, &R); in visitAddExpr()
189 divide(SE, Op, Denominator, &Q, &R); in visitMulExpr()
233 divide(SE, Diff, Denominator, &Q, &R); in visitMulExpr()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dlegalizedag_vec.ll7 ; legalizing the divide in LegalizeDAG, we scalarize the vector divide and make
8 ; two 64 bit divide library calls which introduces i64 nodes that needs to be
H A Dnocf_check.ll46 attributes #0 = { nocf_check noinline nounwind optnone uwtable "correctly-rounded-divide-sqrt-fp-ma…
47 attributes #1 = { noinline nounwind optnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false"…
/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DLowLevelTypeTest.cpp304 EXPECT_EQ(LLT::scalar(16), LLT::scalar(32).divide(2)); in TEST()
305 EXPECT_EQ(LLT::scalar(8), LLT::scalar(32).divide(4)); in TEST()
306 EXPECT_EQ(LLT::scalar(8), LLT::scalar(32).divide(4)); in TEST()
309 EXPECT_EQ(LLT::scalar(32), LLT::pointer(0, 64).divide(2)); in TEST()
312 EXPECT_EQ(LLT::scalar(32), LLT::fixed_vector(2, 32).divide(2)); in TEST()
313 EXPECT_EQ(LLT::fixed_vector(2, 32), LLT::fixed_vector(4, 32).divide(2)); in TEST()
317 LLT::fixed_vector(4, LLT::pointer(1, 64)).divide(4)); in TEST()
319 LLT::fixed_vector(4, LLT::pointer(1, 64)).divide(2)); in TEST()
/llvm-project-15.0.7/compiler-rt/lib/ubsan/
H A Dubsan_checks.inc36 UBSAN_CHECK(IntegerDivideByZero, "integer-divide-by-zero",
37 "integer-divide-by-zero")
38 UBSAN_CHECK(FloatDivideByZero, "float-divide-by-zero", "float-divide-by-zero")
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td16 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
17 def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I
50 def WriteFDiv16 : SchedWrite; // 16-bit floating point divide
51 def WriteFDiv32 : SchedWrite; // 32-bit floating point divide
52 def WriteFDiv64 : SchedWrite; // 64-bit floating point divide
142 def ReadFDiv16 : SchedRead; // 16-bit floating point divide
143 def ReadFDiv32 : SchedRead; // 32-bit floating point divide
144 def ReadFDiv64 : SchedRead; // 64-bit floating point divide
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dmicromips-attr.ll23 "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false"
33 "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false"
/llvm-project-15.0.7/mlir/test/Dialect/Arithmetic/
H A Dexpand-ops.mlir3 // Test ceil divide with signed integer
33 // Test ceil divide with index type
63 // Test floor divide with signed integer
90 // Test floor divide with index type
117 // Test ceil divide with unsigned integer
134 // Test unsigned ceil divide with index
/llvm-project-15.0.7/lld/test/wasm/Inputs/
H A Ddebuginfo1.ll38 attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-c…
39 attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="fa…
40 attributes #2 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "les…
/llvm-project-15.0.7/lld/test/COFF/Inputs/
H A Dundefined-symbol-multi-lto.ll16 attributes #0 = { noinline optnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable…
17 attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "fra…
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dp10-vector-divide.ll12 ; This test case aims to test the vector divide instructions on Power10.
13 ; This includes the low order and extended versions of vector divide,
15 ; This also includes 128 bit vector divide instructions.
57 ; Test the vector divide extended intrinsics.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dclang-section.ll52 attributes #4 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-ma…
53 attributes #5 = { noinline "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="pres…
54 attributes #6 = { "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign…
55 attributes #7 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-ma…
/llvm-project-15.0.7/llvm/test/Transforms/GVNHoist/
H A Dpr30499.ll28 attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="fa…
29 attributes #1 = { nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-c…
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/Windows/
H A Dwineh-basic.ll39 attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="fa…
40 attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "les…
/llvm-project-15.0.7/llvm/test/CodeGen/BPF/BTF/
H A Dstatic-func.ll70 attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="fa…
71 attributes #1 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-c…
72 attributes #2 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "fra…
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dno-vx.ll31 attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disabl…
32 attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "fra…
H A Dsubregliveness-03.ll49 attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "les…
50 attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="fa…
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-storebytesmerge.ll44 attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="fa…
45 attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "les…
/llvm-project-15.0.7/llvm/test/DebugInfo/X86/
H A Dfission-no-inlining.ll25 attributes #0 = { uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="fal…
26 attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "les…
/llvm-project-15.0.7/compiler-rt/test/fuzzer/
H A Dvalue-profile-div.test3 CHECK: AddressSanitizer: {{FPE|int-divide-by-zero}}
/llvm-project-15.0.7/llvm/test/Transforms/Coroutines/
H A Dcoro-split-dbg.ll65 attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-ca…
67 attributes #2 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "les…
68 attributes #3 = { nounwind uwtable presplitcoroutine "correctly-rounded-divide-sqrt-fp-math"="false…
71 attributes #6 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="fa…

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