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/llvm-project-15.0.7/llvm/test/MC/AVR/
H A Dinst-dec.s7 dec r26
8 dec r3
9 dec r24
10 dec r20
12 ; CHECK: dec r26 ; encoding: [0xaa,0x95]
13 ; CHECK: dec r3 ; encoding: [0x3a,0x94]
14 ; CHECK: dec r24 ; encoding: [0x8a,0x95]
17 ; CHECK-INST: dec r26
18 ; CHECK-INST: dec r3
19 ; CHECK-INST: dec r24
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Drd-mod-wr-eflags.ll17 %dec = add i64 %0, -1
18 store i64 %dec, ptr %o, align 8
19 %tobool = icmp eq i64 %dec, 0
55 %dec.i = add nsw i64 %0, -1
84 %dec.i = add nsw i64 %0, -1
102 ; 64 bit dec
122 %dec = add i64 %0, -1
127 ; 32 bit dec
136 ; 16 bit dec
145 ; 8 bit dec
[all …]
H A Dbmi-intrinsics-fast-isel-x86_64.ll49 %dec = sub i64 %a0, 1
50 %res = xor i64 %a0, %dec
60 %dec = sub i64 %a0, 1
61 %res = and i64 %a0, %dec
128 %dec = sub i64 %a0, 1
129 %res = xor i64 %a0, %dec
139 %dec = sub i64 %a0, 1
140 %res = and i64 %a0, %dec
H A Dadd-of-carry.ll34 %dec = sext i1 %cmp to i32
35 %dec.res = add nsw i32 %dec, %res
36 ret i32 %dec.res
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Dfloating-point-small-iv.ll31 %dec.int = add nsw i32 %iv.int, -1
32 %cmp = icmp ugt i32 %dec.int, 0
67 %dec.int = add nsw i32 %iv.int, -1
68 %cmp = icmp ugt i32 %dec.int, 0
106 %dec.int = add nsw i32 %iv.int, -1
107 %cmp = icmp ugt i32 %dec.int, 0
139 %dec.int = add nsw i32 %iv.int, -1
140 %cmp = icmp sgt i32 %dec.int, 0
173 %dec.int = add nsw i32 %iv.int, -1
208 %cmp = icmp ugt i32 %dec.int, 3
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.atomic.dec.ll5 declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #2
6 declare i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) #2
7 declare i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* nocapture, i32, i32, i32, i1) #2
9 declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #2
10 declare i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* nocapture, i64, i32, i32, i1) #2
11 declare i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* nocapture, i64, i32, i32, i1) #2
142 %result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)
153 %result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
162 %result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)
172 %result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/ScalarEvolution/
H A Dnw-sub-is-not-nw-add.ll10 %idx = phi i32 [ 6, %entry ], [ %idx.dec, %loop ]
12 %idx.dec = sub nuw i32 %idx, 1
13 %cond = icmp uge i32 %idx.dec, 5
30 %idx = phi i32 [ -1, %entry ], [ %idx.dec, %loop ]
35 %idx.dec = sub nsw i32 %idx, -2147483648
36 %cond = icmp eq i32 %idx.dec, %lim
H A Dpr22641.ll9 %dec2 = phi i16 [ %a, %entry ], [ %dec, %cond ]
10 %dec = add i16 %dec2, -1
12 %conv = zext i16 %dec to i32
13 ; CHECK: %conv = zext i16 %dec to i32
H A D2008-07-29-SMinExpr.ll12 %j.01 = phi i32 [ %dec, %forinc ], [ -2147483632, %entry ]
13 %dec = add i32 %j.01, -1
16 %cmp5 = icmp sgt i32 %dec, %cond
20 %j.0.lcssa = phi i32 [ -2147483632, %entry ], [ %dec, %forinc ]
/llvm-project-15.0.7/llvm/test/Transforms/InferAddressSpaces/AMDGPU/
H A Dintrinsics.ll55 %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %cast, i32 %val, i32 0, i32 0, i1 false)
63 %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %cast, i32 %val, i32 0, i32 0, i1 false)
71 %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %cast, i64 %y, i32 0, i32 0, i1 false)
79 %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %cast, i64 %y, i32 0, i32 0, i1 false)
97 %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %cast, i32 %val, i32 0, i32 0, i1 true)
106 %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %cast, i32 %val, i32 0, i32 0, i1 true)
112 ; CHECK-NEXT: %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %cast, i64 %y, i32 0, i32 0, i…
115 %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %cast, i64 %y, i32 0, i32 0, i1 true)
124 %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %cast, i64 %y, i32 0, i32 0, i1 true)
132 declare i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* nocapture, i32, i32, i32, i1) #2
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/llvm-project-15.0.7/llvm/test/CodeGen/AVR/
H A Dload.ll66 %y.addr.08 = phi i8 [ %dec, %while.body ], [ %y, %entry ]
68 %dec = add i8 %y.addr.08, -1
72 %tobool = icmp eq i8 %dec, 0
88 %y.addr.04 = phi i16 [ %dec, %while.body ], [ %y, %entry ]
90 %dec = add nsw i16 %y.addr.04, -1
94 %tobool = icmp eq i16 %dec, 0
109 %y.addr.08 = phi i8 [ %dec, %while.body ], [ %y, %entry ]
111 %dec = add i8 %y.addr.08, -1
115 %tobool = icmp eq i8 %dec, 0
133 %dec = add nsw i16 %y.addr.04, -1
[all …]
H A Drot.ll9 ; CHECK-NEXT: dec r22
15 ; CHECK-NEXT: dec r22
36 ; CHECK-NEXT: dec r22
43 ; CHECK-NEXT: dec r22
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dicmp-or.ll241 %dec = add i8 %x, -1
243 %or = or i8 %x, %dec
256 %dec = add i8 %x, -1
257 %or = or i8 %dec, %x
272 %dec = add i8 %x, -1
273 %or = or i8 %dec, %x
287 %dec = add i8 %x, -2
288 %or = or i8 %dec, %x
315 %dec = add i8 %x, -1
317 %or = or i8 %x, %dec
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/X86/
H A Dpr26973.ll16 %iv.outer = phi i32 [ %p1, %entry ], [ %iv.outer.dec, %outer.be ]
23 %iv.inner = phi i32 [ %iv.outer, %outer.loop ], [ %iv.inner.dec, %inner.loop ]
26 %iv.inner.dec = add nsw i32 %iv.inner, -1
27 %cmp = icmp slt i32 %iv.outer, %iv.inner.dec
31 %iv.outer.dec = add nsw i32 %iv.outer, -1
/llvm-project-15.0.7/clang/test/utils/update_cc_test_checks/Inputs/
H A Dglobal-hex-value-regex.c.expected6 // CHECK: @foo.dec = internal global i32 10, align 4
8 // CHECK: @bar.dec = internal global i32 20, align 4
16 static int dec = 10;
24 static int dec = 20;
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/
H A Dscev-after-loopinstsimplify.ll7 ; 1. indvars marks %dec as NUW.
8 ; 2. loop-instsimplify runs instsimplify, which constant-folds %dec to -1
10 ; with an type assertion in cast, because %dec is no longer an Instruction,
26 %c.0 = phi i16 [ 0, %entry ], [ %dec, %land.end ]
41 %dec = add nsw i16 %c.0, -1
/llvm-project-15.0.7/llvm/test/Transforms/LoopInterchange/
H A Dpr43326.ll34 %dec7 = phi i8 [ 0, %for.body ], [ %dec, %for.inc10 ]
58 %dec = add i8 %dec7, -1
59 %cmp = icmp sgt i8 %dec, -1
64 %dec.lcssa = phi i8 [ %dec, %for.inc10 ]
77 %dec.lcssa.lcssa = phi i8 [ %dec.lcssa, %for.inc12 ]
78 store i8 %dec.lcssa.lcssa, i8* @b
/llvm-project-15.0.7/llvm/test/Transforms/IRCE/
H A Dvariable-loop-bounds.ll215 %dec = add nsw i32 %iv, -1
216 %cmp = icmp sgt i32 %dec, %M
252 %dec = add nsw i32 %iv, -1
284 %dec = add nsw i32 %iv, -1
321 %dec = add nsw i32 %iv, -1
322 %cmp = icmp ne i32 %dec, %M
353 %dec = add nsw i32 %iv, -1
354 %cmp = icmp eq i32 %dec, %M
365 %iv = phi i64 [ %dec, %for.dec ], [ 0, %entry ]
370 br label %for.dec
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/
H A Datomics.ll27 ; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %ptr, i32 %…
29 …%ret = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %ptr, i32 %val, i32 0, i32 0, …
33 ; CHECK: DIVERGENT: %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 %…
35 …%ret = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 %val, i32 0, i32 0, …
41 declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #1
42 declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #1
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-trunc-store.ll30 %dec = add nsw i32 %arg, -1
31 %idxprom8 = sext i32 %dec to i64
49 %dec = add nsw i32 %arg, -1
50 %idxprom8 = sext i32 %dec to i64
68 %dec = add nsw i32 %arg, -1
69 %idxprom8 = sext i32 %dec to i64
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dbzip_reverse_loops.ll16 %n.addr.0 = phi i32 [ %n, %entry ], [ %dec, %cond.end ]
32 %dec = add i32 %n.addr.0, -1
33 %tobool = icmp eq i32 %dec, 0
52 %n.addr.0 = phi i32 [ %n, %entry ], [ %dec, %do.body ]
60 %dec = add nsw i32 %n.addr.0, -1
61 %tobool = icmp eq i32 %dec, 0
/llvm-project-15.0.7/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/
H A Datomics.ll27 ; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %ptr, i32 %…
29 …%ret = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %ptr, i32 %val, i32 0, i32 0, …
33 ; CHECK: DIVERGENT: %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 %…
35 …%ret = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 %val, i32 0, i32 0, …
41 declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #1
42 declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #1
/llvm-project-15.0.7/libcxx/test/std/input.output/iostreams.base/ios.base/fmtflags.state/
H A Dsetf_fmtflags_mask.pass.cpp33 assert(t.flags() == (test::skipws | test::dec)); in main()
34 test::fmtflags f = t.setf(test::hex | test::right, test::dec | test::right); in main()
35 assert(f == (test::skipws | test::dec)); in main()
H A Dsetf_fmtflags.pass.cpp33 assert(t.flags() == (test::skipws | test::dec)); in main()
35 assert(f == (test::skipws | test::dec)); in main()
36 assert(t.flags() == (test::skipws | test::dec | test::hex | test::right)); in main()
/llvm-project-15.0.7/llvm/test/Analysis/BasicAA/
H A Dphi-speculation.ll16 %num = phi i32 [ %count, %entry ], [ %dec, %while.body ]
20 %dec = add nsw i32 %num, -1
27 %tobool = icmp eq i32 %dec, 0
57 %num = phi i32 [ %count, %outer.while.header ], [ %dec, %while.body ]
61 %dec = add nsw i32 %num, -1
68 %tobool = icmp eq i32 %dec, 0
80 %dec.outer = add nsw i32 %num.outer, -1
81 %br.cond = icmp eq i32 %dec.outer, 0
96 %num = phi i32 [ %count, %entry ], [ %dec, %while.body ]
101 %dec = add nsw i32 %num, -1
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