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/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmacro-ddiv.s6 ddiv $25,$11
35 ddiv $24,$12
64 ddiv $25,$0
68 ddiv $0,$9
82 ddiv $0,$0
86 ddiv $4,0
90 ddiv $0,0
94 ddiv $4,1
98 ddiv $4,-1
102 ddiv $4,2
[all …]
H A Dmacro-drem.s9 # CHECK-NOTRAP: ddiv $zero, $4, $5 # encoding: [0x1e,0x00,0x85,0x00]
41 # CHECK-NOTRAP: ddiv $zero, $4, $1 # encoding: [0x1e,0x00,0x81,0x00]
46 # CHECK-NOTRAP: ddiv $zero, $4, $1 # encoding: [0x1e,0x00,0x81,0x00]
52 # CHECK-NOTRAP: ddiv $zero, $4, $1 # encoding: [0x1e,0x00,0x81,0x00]
57 # CHECK-NOTRAP: ddiv $zero, $4, $1 # encoding: [0x1e,0x00,0x81,0x00]
62 # CHECK-NOTRAP: ddiv $zero, $4, $1 # encoding: [0x1e,0x00,0x81,0x00]
68 # CHECK-NOTRAP: ddiv $zero, $5, $6 # encoding: [0x1e,0x00,0xa6,0x00]
88 # CHECK-NOTRAP: ddiv $zero, $5, $4 # encoding: [0x1e,0x00,0xa4,0x00]
97 # CHECK-NOTRAP: ddiv $zero, $4, $5 # encoding: [0x1e,0x00,0x85,0x00]
107 # CHECK-NOTRAP: ddiv $zero, $5, $1 # encoding: [0x1e,0x00,0xa1,0x00]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dmips64muldiv.ll54 ; ACC: ddiv $zero, $4, $5
56 ; GPR: ddiv $2, $4, $5
74 ; ACC: ddiv $zero, $4, $5
H A Dmips64instrs.ll117 ; ACCMULDIV: ddiv $zero, $[[T0]], $[[T1]]
121 ; GPRMULDIV: ddiv $2, $[[T0]], $[[T1]]
153 ; ACCMULDIV: ddiv $zero, $4, $5
H A Ddivrem.ll236 ; ACC64: ddiv $zero, $4, $5
239 ; GPR64: ddiv $2, $4, $5
331 ; ACC64: ddiv $zero, $4, $5
343 ; GPR64-DAG: ddiv $2, $4, $5
/llvm-project-15.0.7/clang/test/CodeGen/
H A Darm-float-helpers.c89 double ddiv(double a, double b) { return a / b; } in ddiv() function
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips3.s30 # ddiv has been re-encoded. See valid.s
H A Dinvalid-mips64.s51 # ddiv has been re-encoded. See valid.s
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips64InstrInfo.td318 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
1135 "ddiv\t$rd, $rs, $rt">,
1139 "ddiv\t$rd, $rs, $imm">,
1150 // GAS expands 'div' and 'ddiv' differently when the destination
1152 // form. 'ddiv' gets expanded, while 'div' is not expanded.
1154 def : MipsInstAlias<"ddiv $rs, $rt", (DSDivMacro GPR64Opnd:$rs,
1158 def : MipsInstAlias<"ddiv $rd, $imm", (DSDivIMacro GPR64Opnd:$rd,
H A DMips64r6InstrInfo.td67 class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV, sdiv>;
/llvm-project-15.0.7/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips3.s20 …ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
H A Dinvalid-mips4.s20 …ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
H A Dinvalid-mips5.s24 …ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64/
H A Dvalid-mips64-el.txt83 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
229 0x1e 0x00 0x56 0x03 # CHECK: ddiv $zero, $26, $22
H A Dvalid-mips64.txt130 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
131 0x03 0x56 0x00 0x1e # CHECK: ddiv $zero, $26, $22
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dsdiv.ll286 ; GP64-NEXT: ddiv $zero, $4, $5
293 ; GP64R6-NEXT: ddiv $2, $4, $5
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r2/
H A Dvalid-mips64r2-el.txt91 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
254 0x1e 0x00 0x56 0x03 # CHECK: ddiv $zero, $26, $22
H A Dvalid-mips64r2.txt144 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
145 0x03 0x56 0x00 0x1e # CHECK: ddiv $zero, $26, $22
/llvm-project-15.0.7/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips3.s24 …ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
H A Dinvalid-mips4.s22 …ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
H A Dinvalid-mips5.s26 …ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfloat-helpers.s351 define double @ddiv(double %a, double %b) #0 {
352 ; CHECK-SOFT-LABEL: ddiv:
359 ; CHECK-SOFTFP-LABEL: ddiv:
366 ; CHECK-HARDFP-DP-LABEL: ddiv:
370 ; CHECK-HARDFP-SPONLY-LABEL: ddiv:
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r6/
H A Dvalid-mips64r6-el.txt104 0x9e 0x10 0x64 0x00 # CHECK: ddiv $2, $3, $4
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips3/
H A Dvalid-mips3-el.txt63 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r3/
H A Dvalid-mips64r3.txt141 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
142 0x03 0x56 0x00 0x1e # CHECK: ddiv $zero, $26, $22

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