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/llvm-project-15.0.7/flang/test/Semantics/
H A Ddata05.f9084 …type(t1) :: d5 ! CHECK: d5 (InDataStmt) size=168 offset=720: ObjectEntity type: TYPE(t1(kind=4_1,l… local
85 data d5%j/1/,d5%x/1,2,3,4/,d5%z%re/6./,d5%z%im/7./,d5%t/.false./,d5%c(1:1)/'a'/,d5%c(2:&
86 &2)/'b'/,d5%xp/arr/,d5%ifptr/ifunc2/,d5%rp/rfunc/,d5%xrp/extrfunc/
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dbasic-arm-instructions-v8.1a.s16 vqrdmlsh.f64 d3, d5, d5
72 vqrdmlsh.s16 d7, d6, d5
104 vqrdmlsh.f32 q3, q4, d5[1]
105 vqrdmlsh.f64 d3, d5, d5[0]
H A Dneon-vld-encoding.s12 vld1.16 {d4, d5, d6}, [r3:64]
13 vld1.32 {d5, d6, d7}, [r3]
16 vld1.16 {d4, d5, d6, d7}, [r3:64]
17 vld1.32 {d5, d6, d7, d8}, [r3]
39 vld1.16 {d4, d5, d6}, [r3:64]!
40 vld1.32 {d5, d6, d7}, [r3]!
45 vld1.32 {d5, d6, d7}, [r3], r6
50 vld1.32 {d5, d6, d7, d8}, [r3]!
176 vld3.32 {d5, d7, d9}, [r4]!
243 vld1.8 {d4[], d5[]}, [r1]
[all …]
H A Dneon-mul-encoding.s111 vmul.u32 d5, d4[0]
112 vmul.f32 d6, d5[1]
120 vmul.f32 q6, d5[1]
126 vmul.s32 d5, d4, d3[1]
127 vmul.u32 d4, d5, d4[0]
128 vmul.f32 d3, d6, d5[1]
136 vmul.f32 q3, q6, d5[1]
143 @ CHECK: vmul.i32 d5, d5, d4[0] @ encoding: [0x44,0x58,0xa5,0xf2]
144 @ CHECK: vmul.f32 d6, d6, d5[1] @ encoding: [0x65,0x69,0xa6,0xf2]
152 @ CHECK: vmul.f32 q6, q6, d5[1] @ encoding: [0x65,0xc9,0xac,0xf3]
[all …]
H A Dsingle-precision-fp.s7 vdiv.f64 d4, d5, d6
15 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
23 vnmla.f64 d5, d4, d3
26 vfms.f64 d4, d5, d6
34 @ CHECK-ERRORS-NEXT: vnmla.f64 d5, d4, d3
40 @ CHECK-ERRORS-NEXT: vfms.f64 d4, d5, d6
58 vabs.f64 d4, d5
59 vcmpe.f64 d5, #0
66 @ CHECK-ERRORS-NEXT: vabs.f64 d4, d5
68 @ CHECK-ERRORS-NEXT: vcmpe.f64 d5, #0
[all …]
H A Dthumb-neon-v8.s3 vmaxnm.f32 d4, d5, d1
4 @ CHECK: vmaxnm.f32 d4, d5, d1 @ encoding: [0x05,0xff,0x11,0x4f]
7 vminnm.f32 d5, d4, d30
8 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x24,0xff,0x3e,0x5f]
32 vcvtn.u32.f32 d5, d3
33 @ CHECK: vcvtn.u32.f32 d5, d3 @ encoding: [0xbb,0xff,0x83,0x51]
52 vrintx.f32 d5, d12
53 @ CHECK: vrintx.f32 d5, d12 @ encoding: [0xba,0xff,0x8c,0x54]
H A Dneon-v8.s3 vmaxnm.f32 d4, d5, d1
4 @ CHECK: vmaxnm.f32 d4, d5, d1 @ encoding: [0x11,0x4f,0x05,0xf3]
7 vminnm.f32 d5, d4, d30
8 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x3e,0x5f,0x24,0xf3]
32 vcvtn.u32.f32 d5, d3
33 @ CHECK: vcvtn.u32.f32 d5, d3 @ encoding: [0x83,0x51,0xbb,0xf3]
52 vrintx.f32 d5, d12
53 @ CHECK: vrintx.f32 d5, d12 @ encoding: [0x8c,0x54,0xba,0xf3]
H A Dneont2-minmax-encoding.s6 vmax.s16 d4, d5, d6
14 vmax.s16 d5, d6
38 @ CHECK: vmax.s16 d4, d5, d6 @ encoding: [0x15,0xef,0x06,0x46]
45 @ CHECK: vmax.s16 d5, d5, d6 @ encoding: [0x15,0xef,0x06,0x56]
68 vmin.s16 d4, d5, d6
76 vmin.s16 d5, d6
100 @ CHECK: vmin.s16 d4, d5, d6 @ encoding: [0x15,0xef,0x16,0x46]
107 @ CHECK: vmin.s16 d5, d5, d6 @ encoding: [0x15,0xef,0x16,0x56]
H A Dneon-minmax-encoding.s4 vmax.s16 d4, d5, d6
12 vmax.s16 d5, d6
36 @ CHECK: vmax.s16 d4, d5, d6 @ encoding: [0x06,0x46,0x15,0xf2]
43 @ CHECK: vmax.s16 d5, d5, d6 @ encoding: [0x06,0x56,0x15,0xf2]
66 vmin.s16 d4, d5, d6
74 vmin.s16 d5, d6
98 @ CHECK: vmin.s16 d4, d5, d6 @ encoding: [0x16,0x46,0x15,0xf2]
105 @ CHECK: vmin.s16 d5, d5, d6 @ encoding: [0x16,0x56,0x15,0xf2]
H A Dseh-epilog-sharing.s111 vpush {d1-d5}
112 .seh_save_fregs {d1-d5}
153 vpush {d1-d5}
154 .seh_save_fregs {d1-d5}
H A Dbfloat16-t32-errors.s3 vdot.bf16 d3, d4, d5
11 vdot.bf16 d3, d4, d5[1]
15 vdot.bf16 q0, q1, d5[1]
H A Dbfloat16-a32-errors.s5 vdot.bf16 d3, d4, d5
7 vdot.bf16 d3, d4, d5[1]
8 vdot.bf16 q0, q1, d5[1]
H A Deh-directive-vsave.s50 .vsave {d0, d1, d2, d3, d4, d5, d6, d7}
51 vpush {d0, d1, d2, d3, d4, d5, d6, d7}
52 vpop {d0, d1, d2, d3, d4, d5, d6, d7}
63 .vsave {d2, d3, d4, d5, d6, d7}
64 vpush {d2, d3, d4, d5, d6, d7}
65 vpop {d2, d3, d4, d5, d6, d7}
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Linalg/IR/
H A DLinalgNamedStructuredOps.yaml438 d5)>
440 d5)>
1090 + d4, d2 + d5)>
2065 -> (d4, d5, d3)>
2808 -> (d4, d5)>
2891 -> (d4, d5)>
2970 -> (d4, d5)>
3049 -> (d4, d5)>
3128 -> (d4, d5)>
3207 -> (d4, d5)>
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dha-alignstack.ll11 define dso_local float @f0_0(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
21 define dso_local float @f0_1(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
31 define dso_local float @f0_2(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
41 define dso_local float @f1_0(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
51 define dso_local float @f1_1(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
71 define dso_local float @f2_0(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
81 define dso_local float @f2_1(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
101 … @g0_0(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, %struct.D0 %s.coerc…
111 … @g0_1(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, %struct…
131 … @g1_0(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, %struct.D1 alignsta…
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dartifact-find-value.mir9 liveins: $x0, $x1, $x2, $d0, $d1, $d2, $d3, $d4, $d5, $d6, $d7, $x0
20 ; CHECK: [[COPY8:%[0-9]+]]:_(s64) = COPY $d5
35 %8:_(s64) = COPY $d5
71 ; CHECK: [[COPY8:%[0-9]+]]:_(s64) = COPY $d5
86 %8:_(s64) = COPY $d5
121 ; CHECK: [[COPY8:%[0-9]+]]:_(s64) = COPY $d5
135 %8:_(s64) = COPY $d5
167 ; CHECK: [[COPY8:%[0-9]+]]:_(s64) = COPY $d5
181 %8:_(s64) = COPY $d5
213 ; CHECK: [[COPY8:%[0-9]+]]:_(s64) = COPY $d5
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dgeneralize-named-ops.mlir83 // CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1 + d5, d2 + d6, d3)>
84 // CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d5, d6, d3, d4)>
85 // CHECK-DAG: #[[MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1, d2, d3, d4)>
110 // CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1 + d5 * 2, d2 + d6 *…
111 // CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d5, d6, d3, d4)>
112 // CHECK-DAG: #[[MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1, d2, d3, d4)>
136 // CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1 * 2 + d4, d2 * 2 + d5, …
137 // CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d4, d5, d3)>
138 // CHECK-DAG: #[[MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d2, d3)>
H A Dfuse-with-reshape-by-collapsing.mlir6 #map0 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d0, d1, d2, d3, d4, d5, d6, d7)>
8 #map2 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d3, d4, d5, d6)>
9 #map3 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d0, d1, d2, d3, d4, d5, d6, d7)>
57 #map0 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d0, d1, d2, d3, d4, d5, d6, d7)>
59 #map2 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d3, d4, d5, d6)>
60 #map3 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d0, d1, d2, d3, d4, d5, d6, d7)>
119 #map0 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d7, d5, d6, d0, d1, d2, d3, d4)>
120 #map1 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d5, d6, d0)>
122 #map3 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d0, d1, d2, d3, d4, d5, d6, d7)>
163 #map0 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d7, d5, d6, d0, d1, d2, d3, d4)>
[all …]
/llvm-project-15.0.7/llvm/test/MC/M68k/ShiftRotate/Classes/
H A DMxSR_DD.s15 ; CHECK: asr.b %d4, %d5
17 asr.b %d4, %d5
18 ; CHECK: asr.l %d5, %d6
20 asr.l %d5, %d6
/llvm-project-15.0.7/llvm/test/MC/Disassembler/M68k/
H A Darithmetic.txt20 # CHECK: add.w (30600,%a4), %d5
26 # CHECK: add.w %d2, (20,%a6,%d5)
59 # CHECK: add.l (4660,%sp), %d5
80 # CHECK: cmp.b %d5, %d7
119 # CHECK: sub.w %d5, (16,%a3,%a2)
149 # CHECK: sub.l %d2, %d5
152 # CHECK: sub.l %a2, %d5
158 # CHECK: subx.l %d5, %d3
200 # CHECK: or.w %d2, %d5
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Dldp-postind.predictable.txt12 # d5 != x5 so "ldp d5, d6, [x5], #24" is fine.
14 # CHECK: ldp d5, d6, [x5], #24
H A Dldp-preind.predictable.txt12 # d5 != x5 so "ldp d5, d6, [x5, #24]!" is fine.
14 # CHECK: ldp d5, d6, [x5, #24]!
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dpseudo_cmov_lower2.ll17 %d5 = fsub double %d2, %d3
18 %d6 = fadd double %d5, %d4
52 %d5 = fsub double %d2, %d3
53 %d6 = fadd double %d5, %d4
80 %d5 = fdiv double %d4, %d3
81 ret double %d5
112 %d5 = fdiv double %d4, %d3
113 ret double %d5
145 %d5 = fsub double %d2, %d3
146 %d6 = fadd double %d5, %d4
[all …]
H A Dpseudo_cmov_lower1.ll17 %d5 = fsub double %d2, %d3
18 %d6 = fadd double %d5, %d4
35 %d5 = fsub float %d2, %d3
36 %d6 = fadd float %d5, %d4
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dbfloat16-t32.txt6 # CHECK: vdot.bf16 d3, d4, d5
10 # CHECK: vdot.bf16 d3, d4, d5[1]
13 # CHECK: vdot.bf16 q0, q1, d5[1]

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