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/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dneon-bitwise-encoding.s176 vand d4, d7, d3
177 vand.8 d4, d7, d3
178 vand.16 d4, d7, d3
179 vand.32 d4, d7, d3
180 vand.64 d4, d7, d3
182 vand.i8 d4, d7, d3
187 vand.s8 d4, d7, d3
202 vand.f d4, d7, d3
203 vand.d d4, d7, d3
234 vorr d4, d7, d3
[all …]
H A Dneon-vld-vst-align.s2978 vld3.8 {d0, d2, d4}, [r4]
3000 vld3.8 {d0, d2, d4}, [r4]!
3326 vld3.16 {d0, d2, d4}, [r4]
3348 vld3.16 {d0, d2, d4}, [r4]!
3745 vld3.32 {d0, d2, d4}, [r4]
3767 vld3.32 {d0, d2, d4}, [r4]!
6925 vst3.8 {d0, d2, d4}, [r4]
6947 vst3.8 {d0, d2, d4}, [r4]!
7129 vst3.16 {d0, d2, d4}, [r4]
7151 vst3.16 {d0, d2, d4}, [r4]!
[all …]
H A Dneon-mul-encoding.s106 vmul.i16 d0, d4[2]
110 vmul.s32 d4, d3[1]
111 vmul.u32 d5, d4[0]
114 vmul.i16 q0, d4[2]
119 vmul.u32 q5, d4[0]
122 vmul.i16 d9, d0, d4[2]
126 vmul.s32 d5, d4, d3[1]
127 vmul.u32 d4, d5, d4[0]
130 vmul.i16 q9, q0, d4[2]
142 @ CHECK: vmul.i32 d4, d4, d3[1] @ encoding: [0x63,0x48,0xa4,0xf2]
[all …]
H A Dneon-vld-encoding.s12 vld1.16 {d4, d5, d6}, [r3:64]
15 vld1.8 {d1, d2, d3, d4}, [r3]
16 vld1.16 {d4, d5, d6, d7}, [r3:64]
39 vld1.16 {d4, d5, d6}, [r3:64]!
48 vld1.8 {d1, d2, d3, d4}, [r3]!
124 vld2.8 {d4-d7}, [r0:64]!
131 vld2.8 {d4-d7}, [r0:64], r6
240 vld1.8 {d4[]}, [r1]
241 vld1.8 {d4[]}, [r1]!
242 vld1.8 {d4[]}, [r1], r3
[all …]
H A Dfp-armv8.s38 vcvtp.s32.f64 s0, d4
39 @ CHECK: vcvtp.s32.f64 s0, d4 @ encoding: [0xc4,0x0b,0xbe,0xfe]
55 vcvtp.u32.f64 s0, d4
74 vseleq.f64 d2, d4, d8
89 vminnm.f64 d4, d6, d9
109 vrinta.f64 d3, d4
110 @ CHECK: vrinta.f64 d3, d4 @ encoding: [0x44,0x3b,0xb8,0xfe]
113 vrintn.f64 d3, d4
114 @ CHECK: vrintn.f64 d3, d4 @ encoding: [0x44,0x3b,0xb9,0xfe]
117 vrintp.f64 d3, d4
[all …]
H A Dthumb-fp-armv8.s41 vcvtp.s32.f64 s0, d4
42 @ CHECK: vcvtp.s32.f64 s0, d4 @ encoding: [0xbe,0xfe,0xc4,0x0b]
58 vcvtp.u32.f64 s0, d4
77 vseleq.f64 d2, d4, d8
92 vminnm.f64 d4, d6, d9
115 vrinta.f64 d3, d4
116 @ CHECK: vrinta.f64 d3, d4 @ encoding: [0xb8,0xfe,0x44,0x3b]
119 vrintn.f64 d3, d4
120 @ CHECK: vrintn.f64 d3, d4 @ encoding: [0xb9,0xfe,0x44,0x3b]
123 vrintp.f64 d3, d4
[all …]
H A Dfp-armv8-m.s45 vcvtp.s32.f64 s0, d4
62 vcvtp.u32.f64 s0, d4
81 vseleq.f64 d2, d4, d8
96 vminnm.f64 d4, d6, d9
120 vrinta.f64 d3, d4
121 @ CHECK-V81M: vrinta.f64 d3, d4 @ encoding: [0xb8,0xfe,0x44,0x3b]
124 vrintn.f64 d3, d4
125 @ CHECK-V81M: vrintn.f64 d3, d4 @ encoding: [0xb9,0xfe,0x44,0x3b]
128 vrintp.f64 d3, d4
129 @ CHECK-V81M: vrintp.f64 d3, d4 @ encoding: [0xba,0xfe,0x44,0x3b]
[all …]
H A Dneon-shift-encoding.s402 @ CHECK: vshl.s8 d4, d4, d5 @ encoding: [0x04,0x44,0x05,0xf2]
403 @ CHECK: vshl.s16 d4, d4, d5 @ encoding: [0x04,0x44,0x15,0xf2]
404 @ CHECK: vshl.s32 d4, d4, d5 @ encoding: [0x04,0x44,0x25,0xf2]
405 @ CHECK: vshl.s64 d4, d4, d5 @ encoding: [0x04,0x44,0x35,0xf2]
407 @ CHECK: vshl.u8 d4, d4, d5 @ encoding: [0x04,0x44,0x05,0xf3]
408 @ CHECK: vshl.u16 d4, d4, d5 @ encoding: [0x04,0x44,0x15,0xf3]
409 @ CHECK: vshl.u32 d4, d4, d5 @ encoding: [0x04,0x44,0x25,0xf3]
410 @ CHECK: vshl.u64 d4, d4, d5 @ encoding: [0x04,0x44,0x35,0xf3]
427 @ CHECK: vshl.i8 d4, d4, #6 @ encoding: [0x14,0x45,0x8e,0xf2]
428 @ CHECK: vshl.i16 d4, d4, #10 @ encoding: [0x14,0x45,0x9a,0xf2]
[all …]
H A Dsingle-precision-fp.s6 vsub.f64 d2, d3, d4
7 vdiv.f64 d4, d5, d6
13 @ CHECK-ERRORS-NEXT: vsub.f64 d2, d3, d4
15 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
23 vnmla.f64 d5, d4, d3
26 vfms.f64 d4, d5, d6
40 @ CHECK-ERRORS-NEXT: vfms.f64 d4, d5, d6
58 vabs.f64 d4, d5
66 @ CHECK-ERRORS-NEXT: vabs.f64 d4, d5
80 vcvt.s32.f64 s5, d4
[all …]
H A Deh-directive-vsave.s50 .vsave {d0, d1, d2, d3, d4, d5, d6, d7}
51 vpush {d0, d1, d2, d3, d4, d5, d6, d7}
52 vpop {d0, d1, d2, d3, d4, d5, d6, d7}
63 .vsave {d2, d3, d4, d5, d6, d7}
64 vpush {d2, d3, d4, d5, d6, d7}
65 vpop {d2, d3, d4, d5, d6, d7}
H A Dsimple-fp-encoding.s159 vmov.f64 d4, r3, r9
164 @ CHECK: vmov d4, r3, r9 @ encoding: [0x14,0x3b,0x49,0xec]
281 @ CHECK: vstr d4, [r1] @ encoding: [0x00,0x4b,0x81,0xed]
282 @ CHECK: vstr d4, [r1, #24] @ encoding: [0x06,0x4b,0x81,0xed]
283 @ CHECK: vstr d4, [r1, #-24] @ encoding: [0x06,0x4b,0x01,0xed]
287 vstr.64 d4, [r1]
288 vstr.64 d4, [r1, #24]
289 vstr.64 d4, [r1, #-24]
313 fldmiaxeq r0, {d4,d5}
314 fldmdbxne r5!, {d4,d5,d6}
[all …]
/llvm-project-15.0.7/llvm/test/TableGen/
H A Dforeach-eval.td10 def d4;
15 !subst(d4, d0, tmp)))));
21 !subst(d4, d0, tmp))))));
27 def d : D <(d0 d1, d2, d3, d4)>;
49 !subst(d4, d0, tmp)))))]>;
55 !subst(d4, d0, t1))))))>;
58 def j1 : J1< (d1 d2:$dst, (d3 d4:$src1))>;
61 def j2 : J2< [(d1 d2:$dst, (d3 d4:$src1))]>;
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dswift-vldm.ll9 ; CHECK: vldmia r{{[0-9]+}}, {d2, d3, d4}
10 ; CHECK-NOT: vldmia r{{[0-9]+}}, {d1, d2, d3, d4}
12 declare fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
23 %d4 = load double , double * %addr3
24 ; We are trying to force x[0-3] in registers d1 to d4 so that we can test we
25 ; don't form a "vldmia rX, {d1, d2, d3, d4}".
28 call fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
H A Dha-alignstack.ll11 define dso_local float @f0_0(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
21 define dso_local float @f0_1(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
31 define dso_local float @f0_2(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
41 define dso_local float @f1_0(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
71 define dso_local float @f2_0(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
81 define dso_local float @f2_1(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
101 define dso_local double @g0_0(double %d0, double %d1, double %d2, double %d3, double %d4, double %d…
111 define dso_local double @g0_1(double %d0, double %d1, double %d2, double %d3, double %d4, double %d…
131 define dso_local double @g1_0(double %d0, double %d1, double %d2, double %d3, double %d4, double %d…
167 ; CHECK: vmov.f64 d0, d4
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dgeneralize-named-ops.mlir83 // CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1 + d5, d2 + d6, d3)>
84 // CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d5, d6, d3, d4)>
85 // CHECK-DAG: #[[MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1, d2, d3, d4)>
111 // CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d5, d6, d3, d4)>
112 // CHECK-DAG: #[[MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1, d2, d3, d4)>
136 // CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1 * 2 + d4, d2 * 2 + d5, …
137 // CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d4, d5, d3)>
138 // CHECK-DAG: #[[MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d2, d3)>
162 // CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2, d3, d4) -> (d0, d1 + d3, d4)>
163 // CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4) -> (d3, d4, d2)>
[all …]
H A Dfuse-with-reshape-by-collapsing.mlir6 #map0 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d0, d1, d2, d3, d4, d5, d6, d7)>
8 #map2 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d3, d4, d5, d6)>
9 #map3 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d0, d1, d2, d3, d4, d5, d6, d7)>
27 // CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2, d3, d4) -> (d0, d1, d2, d3, d4)>
57 #map0 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d0, d1, d2, d3, d4, d5, d6, d7)>
59 #map2 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d3, d4, d5, d6)>
60 #map3 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d0, d1, d2, d3, d4, d5, d6, d7)>
121 #map2 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d4, d1, d2, d3)>
140 // CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2, d3, d4) -> (d4, d3, d0, d1, d2)>
143 // CHECK-DAG: #[[MAP3:.+]] = affine_map<(d0, d1, d2, d3, d4) -> (d0, d1, d2, d3, d4)>
[all …]
/llvm-project-15.0.7/llvm/unittests/ADT/
H A DPointerUnionTest.cpp27 PU4 i4, f4, l4, d4; member
55 EXPECT_TRUE(l4 != d4); in TEST_F()
84 EXPECT_FALSE(d4.isNull()); in TEST_F()
104 EXPECT_TRUE(d4.is<double *>()); in TEST_F()
171 EXPECT_TRUE(isa<double *>(d4)); in TEST_F()
195 EXPECT_FALSE(isa<int *>(d4)); in TEST_F()
196 EXPECT_FALSE(isa<float *>(d4)); in TEST_F()
197 EXPECT_FALSE(isa<long long *>(d4)); in TEST_F()
221 EXPECT_EQ(cast<double *>(d4), &d); in TEST_F()
253 EXPECT_EQ(dyn_cast<int *>(d4), nullptr); in TEST_F()
[all …]
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Linalg/IR/
H A DLinalgNamedStructuredOps.yaml442 d4)>
1090 + d4, d2 + d5)>
1175 + d3 * s4, d4)>
1972 + d4 * s4, d2)>
2808 -> (d4, d5)>
2891 -> (d4, d5)>
2970 -> (d4, d5)>
3049 -> (d4, d5)>
3128 -> (d4, d5)>
3207 -> (d4, d5)>
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dartifact-find-value.mir9 liveins: $x0, $x1, $x2, $d0, $d1, $d2, $d3, $d4, $d5, $d6, $d7, $x0
19 ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $d4
34 %7:_(s64) = COPY $d4
70 ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $d4
85 %7:_(s64) = COPY $d4
120 ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $d4
134 %7:_(s64) = COPY $d4
166 ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $d4
180 %7:_(s64) = COPY $d4
212 ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $d4
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Cortex/
H A Dforwarding-A57.s321 fmul d4, d5, d6
322 fmadd d1, d2, d3, d4
326 fmul d4, d5, d6
327 fmadd d1, d2, d3, d4
331 fmadd d4, d5, d6, d7
332 fmadd d1, d2, d3, d4
336 fmsub d4, d5, d6, d7
337 fmsub d1, d2, d3, d4
341 fnmadd d4, d5, d6, d7
342 fnmadd d1, d2, d3, d4
[all …]
/llvm-project-15.0.7/llvm/test/MC/M68k/ShiftRotate/Classes/
H A DMxSR_DD.s12 ; CHECK: lsr.l %d3, %d4
14 lsr.l %d3, %d4
15 ; CHECK: asr.b %d4, %d5
17 asr.b %d4, %d5
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dfp-armv8.txt44 # CHECK: vcvtp.s32.f64 s0, d4
68 # CHECK: vcvtp.u32.f64 s0, d4
93 # CHECK: vseleq.f64 d2, d4, d8
112 # CHECK: vminnm.f64 d4, d6, d9
134 # CHECK: vrinta.f64 d3, d4
140 # CHECK: vrintn.f64 d3, d4
146 # CHECK: vrintp.f64 d3, d4
152 # CHECK: vrintm.f64 d3, d4
H A Dthumb-fp-armv8.txt48 # CHECK: vcvtp.s32.f64 s0, d4
72 # CHECK: vcvtp.u32.f64 s0, d4
97 # CHECK: vseleq.f64 d2, d4, d8
116 # CHECK: vminnm.f64 d4, d6, d9
142 # CHECK: vrinta.f64 d3, d4
148 # CHECK: vrintn.f64 d3, d4
154 # CHECK: vrintp.f64 d3, d4
160 # CHECK: vrintm.f64 d3, d4
/llvm-project-15.0.7/llvm/test/MC/Disassembler/M68k/
H A Darithmetic.txt98 # CHECK: or.l (%a3), %d4
116 # CHECK: or.b #16, (3,%a3,%d4)
125 # CHECK: suba.l %d4, %a1
131 # CHECK: add.w %d0, %d4
146 # CHECK: sub.w %d2, %d4
155 # CHECK: subx.w %d2, %d4
161 # CHECK: suba.l %d4, %a0
182 # CHECK: and.w (288,%a2), %d4
188 # CHECK: and.l #100, (1,%a1,%d4)
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dconstant-expression-cxx1z.cpp22 constexpr D d4 = {}; variable
23 static_assert(d4.a == 10 && d4.b == 30 && d4.c == 29 && d4.q == 0 && d4.k == 0);

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