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/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dvpush-vpop.s6 vpush {d8, d9, d10, d11, d12}
8 vpop {d8, d9, d10, d11, d12}
11 vpush.s8 {d8, d9, d10, d11, d12}
13 vpop.f32 {d8, d9, d10, d11, d12}
16 @ CHECK-THUMB: vpush {d8, d9, d10, d11, d12} @ encoding: [0x2d,0xed,0x0a,0x8b]
18 @ CHECK-THUMB: vpop {d8, d9, d10, d11, d12} @ encoding: [0xbd,0xec,0x0a,0x8b]
21 @ CHECK-ARM: vpush {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0x2d,0xed]
23 @ CHECK-ARM: vpop {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0xbd,0xec]
26 @ CHECK-THUMB: vpush {d8, d9, d10, d11, d12} @ encoding: [0x2d,0xed,0x0a,0x8b]
31 @ CHECK-ARM: vpush {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0x2d,0xed]
[all …]
H A Deh-directive-integrated-test.s40 .vsave {d8, d9, d10, d11, d12}
41 vpush {d8, d9, d10, d11, d12}
45 vpop {d8, d9, d10, d11, d12}
74 .vsave {d8, d9, d10, d11, d12}
75 vpush {d8, d9, d10, d11, d12}
79 vpop {d8, d9, d10, d11, d12}
H A Dsingle-precision-fp.s9 vnmul.f64 d8, d9, d10
19 @ CHECK-ERRORS-NEXT: vnmul.f64 d8, d9, d10
21 vmla.f64 d11, d10, d9
28 vfnms.f64 d10, d11, d12
30 @ CHECK-ERRORS-NEXT: vmla.f64 d11, d10, d9
44 @ CHECK-ERRORS-NEXT: vfnms.f64 d10, d11, d12
74 vmov.f64 d11, d10
76 @ CHECK-ERRORS-NEXT: vmov.f64 d11, d10
87 vcvt.u32.f64 d9, d10, #4
111 @ CHECK-ERRORS-NEXT: vcvt.u32.f64 d9, d10, #4
H A Dneont2-dup-encoding.s22 vdup.8 q3, d10[0]
28 vdup.8 q3, d10[1]
35 @ CHECK: vdup.8 q3, d10[0] @ encoding: [0xb1,0xff,0x4a,0x6c]
41 @ CHECK: vdup.8 q3, d10[1] @ encoding: [0xb3,0xff,0x4a,0x6c]
H A Dneon-bitwise-encoding.s64 vand.i16 d10, #0xff03
66 vand.i16 d10, #0x03ff
68 vand.i32 d10, #0x03ffffff
70 vand.i32 d10, #0xff03ffff
72 vand.i32 d10, #0xffff03ff
74 vand.i32 d10, #0xffffff03
77 @ CHECK: vbic.i16 d10, #0xfc @ encoding: [0x3c,0xa9,0x87,0xf3]
79 @ CHECK: vbic.i16 d10, #0xfc00 @ encoding: [0x3c,0xab,0x87,0xf3]
83 @ CHECK: vbic.i32 d10, #0xfc0000 @ encoding: [0x3c,0xa5,0x87,0xf3]
85 @ CHECK: vbic.i32 d10, #0xfc00 @ encoding: [0x3c,0xa3,0x87,0xf3]
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dneon-scalar-shift-imm.s15 ushr d10, d17, #18
57 ursra d18, d10, #13
64 shl d7, d10, #12
110 sri d10, d12, #14
117 sli d10, d14, #12
126 sqshrn s18, d10, #31
159 uqrshrn s10, d10, #25
H A Dseh-packed-unwind.s327 stp d10, d11, [sp, #96]
328 .seh_save_fregp d10, 96
344 ldp d10, d11, [sp, #96]
345 .seh_save_fregp d10, 96
370 str d10, [sp, #40]
371 .seh_save_freg d10, 40
379 ldr d10, [sp, #40]
380 .seh_save_freg d10, 40
397 stp d10, d11, [sp, #24]
637 .seh_save_freg d10, 24
[all …]
H A Darm64-memory.s287 ldp d10, d1, [x2]
295 ; CHECK: ldp d10, d1, [x2] ; encoding: [0x4a,0x04,0x40,0x6d]
301 stp d10, d1, [x2]
307 ; CHECK: stp d10, d1, [x2] ; encoding: [0x4a,0x04,0x00,0x6d]
319 ldp d10, d1, [x2, #16]!
326 ; CHECK: ldp d10, d1, [x2, #16]! ; encoding: [0x4a,0x04,0xc1,0x6d]
331 stp d10, d1, [x2, #16]!
347 ldp d10, d1, [x2], #16
359 stp d10, d1, [x2], #16
373 ldnp d10, d1, [x2]
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/
H A Dcortex-a57-neon-instructions.s957 vst2.8 {d8, d10}, [r4]!
958 vst2.16 {d8, d10}, [r4]!
959 vst2.32 {d8, d10}, [r4]!
988 vst2.16 {d8, d10}, [r4]
989 vst2.32 {d8, d10}, [r4]
990 vst2.8 {d8, d10}, [r4]
1041 vld2.8 {d8, d10}, [r4]!
1042 vld2.16 {d8, d10}, [r4]!
1072 vld2.16 {d8, d10}, [r4]
1073 vld2.32 {d8, d10}, [r4]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Daligned-spill.ll17 …tail call void asm sideeffect "", "~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15}"() nounwi…
29 ; NEON: vst1.64 {d8, d9, d10, d11}, [r4:128]!
39 ; NEON: vld1.64 {d8, d9, d10, d11}, [r[[R4]]:128]!
50 tail call void asm sideeffect "", "~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14}"() nounwind
60 ; NEON: vst1.64 {d8, d9, d10, d11}, [r4:128]!
64 ; NEON: vld1.64 {d8, d9, d10, d11},
74 tail call void asm sideeffect "", "~{d8},~{d9},~{d10},~{d12},~{d13},~{d14},~{d15}"() nounwind
88 ; NEON: vstr d10, [r4, #16]
91 ; NEON: vldr d10, [{{.*}}, #16]
H A Dmve-nofloat.ll13 ; CHECK-NOFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
14 ; CHECK-NOFP-NEXT: vpush {d8, d9, d10, d11, d12, d13}
90 ; CHECK-NOFP-NEXT: vpop {d8, d9, d10, d11, d12, d13}
107 ; CHECK-NOFP-NEXT: .vsave {d8, d9, d10, d11}
108 ; CHECK-NOFP-NEXT: vpush {d8, d9, d10, d11}
119 ; CHECK-NOFP-NEXT: vmov r4, r0, d10
128 ; CHECK-NOFP-NEXT: vpop {d8, d9, d10, d11}
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dneont2.txt1686 # CHECK: vst1.8 {d8, d9, d10}, [r4]!
1694 # CHECK: vst1.8 {d8, d9, d10}, [r4], r6
1733 # CHECK: vst2.8 {d8, d10}, [r4]!
1739 # CHECK: vst2.8 {d8, d10}, [r4], r6
1746 # CHECK: vst3.8 {d8, d9, d10}, [r4]!
1799 # CHECK: vst2.16 {d8, d10}, [r4]
1801 # CHECK: vst2.32 {d8, d10}, [r4]
1803 # CHECK: vst2.8 {d8, d10}, [r4]
1806 # CHECK: vst3.8 {d8, d9, d10}, [r4]
1808 # CHECK: vst3.16 {d8, d9, d10}, [r4]
[all …]
H A Dneon.txt1979 # CHECK: vst1.8 {d8, d9, d10}, [r4]!
1987 # CHECK: vst1.8 {d8, d9, d10}, [r4], r6
2026 # CHECK: vst2.8 {d8, d10}, [r4]!
2032 # CHECK: vst2.8 {d8, d10}, [r4], r6
2039 # CHECK: vst3.8 {d8, d9, d10}, [r4]!
2098 # CHECK: vst2.8 {d8, d10}, [r4]
2101 # CHECK: vst3.8 {d8, d9, d10}, [r4]
2115 # CHECK: vst3.8 {d8, d10, d12}, [r4]
2162 # CHECK: vld1.8 {d8, d9, d10}, [r4]!
2170 # CHECK: vld1.8 {d8, d9, d10}, [r4], r6
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dwineh-frame2.mir9 # CHECK-NEXT: frame-setup STPDi killed $d10, killed $d11, $sp, 3
17 # CHECK-NEXT: $d10, $d11 = frame-destroy LDPDi $sp, 3
62 liveins: $x0, $x1, $d0, $d1, $d10, $d11, $d8, $d9
66 $d10 = FADDDrr $d9, $d8
67 $d11 = FADDDrr killed $d9, $d10
H A Dwineh-frame4.mir7 # CHECK-NEXT: frame-setup STRDui killed $d10, $sp, 1 :: (store (s64) into %stack.0)
11 # CHECK-NEXT: $d10 = frame-destroy LDRDui $sp, 1 :: (load (s64) from %stack.0)
56 $d10 = FADDDrr killed $d8, $d0
57 $x0 = COPY killed $d10
H A Dwineh-frame1.mir17 # CHECK-NEXT: frame-setup STPDi killed $d10, killed $d11, $sp, 12
21 # CHECK-NEXT: $d10, $d11 = frame-destroy LDPDi $sp, 12
74 …liveins: $x0, $x1, $d0, $d1, $d10, $d11, $d8, $d9, $x27, $x28, $x25, $x26, $x23, $x24, $x21, $x22,…
79 $d10 = FADDDrr $d9, $d8
80 $d11 = FADDDrr killed $d9, $d10
H A Daarch64-dynamic-stack-layout.ll28 ; return i10 + (int)d10 + l1 + g();
35 ; return i10 + (int)d10 + l1;
42 ; return i10 + (int)d10 + l1 + g();
49 ; return i10 + (int)d10 + l1;
90 %conv = fptosi double %d10 to i32
150 %conv = fptosi double %d10 to i32
172 %conv = fptosi double %d10 to i32
245 %conv = fptosi double %d10 to i32
276 %conv = fptosi double %d10 to i32
334 %conv = fptosi double %d10 to i32
[all …]
H A Darm64-register-pairing.ll12 ; CHECK-NEXT: stp d11, d10, [sp, #32] ; 16-byte Folded Spill
28 ; CHECK-NEXT: ldp d11, d10, [sp, #32] ; 16-byte Folded Reload
36 ; CHECK-NOTMACHO-NEXT: stp d10, d8, [sp, #16] // 16-byte Folded Spill
45 ; CHECK-NOTMACHO-NEXT: ldp d10, d8, [sp, #16] // 16-byte Folded Reload
50 …call void asm sideeffect "mov x0, #42", "~{x0},~{x19},~{x21},~{x23},~{x25},~{x27},~{d8},~{d10},~{d…
59 ; CHECK-NEXT: stp d11, d10, [sp, #32] ; 16-byte Folded Spill
75 ; CHECK-NEXT: ldp d11, d10, [sp, #32] ; 16-byte Folded Reload
H A Dwineh8.mir20 # CHECK-NEXT: 0xda8d ; stp d10, d11, [sp, #-112]!
33 # CHECK-NEXT: 0xda8d ; ldp d10, d11, [sp], #112
47 # CHECK-NEXT: 0xda8d ; ldp d10, d11, [sp], #112
124 stack-id: default, callee-saved-register: '$d10', callee-saved-restored: true,
133 …liveins: $x0, $x1, $d0, $d1, $d10, $d11, $d8, $d9, $x27, $x28, $x25, $x26, $x23, $x24, $x21, $x22,…
135 …early-clobber $sp = frame-setup STPDpre killed $d10, killed $d11, $sp, -14 :: (store (s64) into %s…
168 $d10 = FADDDrr $d9, $d8
169 $d11 = FADDDrr killed $d9, $d10
199 …early-clobber $sp, $d10, $d11 = frame-destroy LDPDpost $sp, 14 :: (load (s64) from %stack.12), (lo…
220 …early-clobber $sp, $d10, $d11 = frame-destroy LDPDpost $sp, 14 :: (load (s64) from %stack.12), (lo…
H A Dwineh4.mir20 # CHECK-NEXT: 0xda8d ; stp d10, d11, [sp, #-112]!
34 # CHECK-NEXT: 0xda8d ; ldp d10, d11, [sp], #112
48 # CHECK-NEXT: 0xda8d ; ldp d10, d11, [sp], #112
125 stack-id: default, callee-saved-register: '$d10', callee-saved-restored: true,
134 …liveins: $x0, $x1, $d0, $d1, $d10, $d11, $d8, $d9, $x27, $x28, $x25, $x26, $x23, $x24, $x21, $x22,…
136 …early-clobber $sp = frame-setup STPDpre killed $d10, killed $d11, $sp, -14 :: (store (s64) into %s…
169 $d10 = FADDDrr $d9, $d8
170 $d11 = FADDDrr killed $d9, $d10
200 …early-clobber $sp, $d10, $d11 = frame-destroy LDPDpost $sp, 14 :: (load (s64) from %stack.12), (lo…
223 …early-clobber $sp, $d10, $d11 = frame-destroy LDPDpost $sp, 14 :: (load (s64) from %stack.12), (lo…
H A Dwineh2.mir20 # CHECK-NEXT: 0xd882 ; stp d10, d11, [sp, #16]
32 # CHECK-NEXT: 0xd882 ; ldp d10, d11, [sp, #16]
108 stack-id: default, callee-saved-register: '$d10', callee-saved-restored: true,
119 …liveins: $x0, $x1, $d0, $d1, $d8, $d9, $d10, $d11, $d12, $x19, $x20, $x21, $x22, $x23, $x24, $x25,…
123 …frame-setup STPDi killed $d10, killed $d11, $sp, 2 :: (store (s64) into %stack.12), (store (s64) i…
143 $d10 = FADDDrr $d9, $d8
144 $d11 = FADDDrr killed $d9, $d10
145 $d12 = FADDDrr killed $d10, killed $d11
172 …$d10, $d11 = frame-destroy LDPDi $sp, 2 :: (load (s64) from %stack.12), (load (s64) from %stack.13)
H A Darm64-homogeneous-prolog-epilog-frame-tail.ll52 ; CHECK: stp d11, d10, [sp, #-48]!
62 ; CHECK-NEXT: ldp d11, d10, [sp], #64
70 ; CHECK-LINUX: stp d11, d10, [sp, #-32]!
80 ; CHECK-LINUX-NEXT: ldp d11, d10, [sp], #64
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A D2010-12-07-PEIBug.ll8 ; CHECK-NEXT: vpush {d10, d11}
10 tail call void asm sideeffect "","~{d8},~{d10},~{d11}"() nounwind
12 ; CHECK-NEXT: vpop {d10, d11}
H A Dv6-jumptable-clobber.mir37 i32 9, label %d10
77 d10: ; preds = %0
115 i32 9, label %d10
155 d10: ; preds = %0
224 '%bb.11.d10', '%bb.2.d1', '%bb.2.d1', '%bb.2.d1',
243 … %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.…
267 bb.11.d10:
322 '%bb.11.d10', '%bb.2.d1', '%bb.2.d1', '%bb.2.d1',
340 … %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.…
364 bb.11.d10:
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfp128-calling-conv.ll10 …, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d9, fp128 %d10, fp128 %d11, fp128 …
18 …, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d9, fp128 %d10, fp128 %d11, fp128 …
27 …, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d9, fp128 %d10, fp128 %d11, fp128 …
36 …, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d9, fp128 %d10, fp128 %d11, fp128 …
45 …, fp128 %d4, fp128 %d5, fp128 %d6, fp128 %d7, fp128 %d8, fp128 %d9, fp128 %d10, fp128 %d11, fp128 …

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