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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCScheduleP10.td120 // A BR pipeline may take 2 cycles to complete.
125 // A CY pipeline may take 7 cycles to complete.
268 // A DX pipeline may take 5 cycles to complete.
273 // A F2 pipeline may take 4 cycles to complete.
287 // A LD pipeline may take 6 cycles to complete.
292 // A MF pipeline may take 13 cycles to complete.
302 // A MM pipeline may take 10 cycles to complete.
307 // A MU pipeline may take 5 cycles to complete.
312 // A PM pipeline may take 4 cycles to complete.
317 // A ST pipeline may take 3 cycles to complete.
[all …]
H A DPPCScheduleP9.td19 // Load latency is 4 or 5 cycles depending on the load. This latency assumes
23 // of instructions are 4 or 5 cycles.
26 // A total of 16 cycles to recover from a branch mispredict.
190 // An ALU may take either 2 or 3 cycles to complete the operation.
218 // A DIV unit may take from 5 to 40 cycles to complete.
219 // Some DIV operations may keep the unit busy for up to 8 cycles.
244 // A DP unit may take from 2 to 36 cycles to complete.
245 // Some DP operations keep the unit busy for up to 10 cycles.
329 // Loads can have 4, 5 or 6 cycles of latency.
352 // Can take from 12 cycles to 76 cycles to obtain a result.
[all …]
/llvm-project-15.0.7/lldb/scripts/
H A Danalyze-project-deps.py85 def is_existing_cycle(path, cycles): argument
106 if is_existing_cycle(cur_path, cycles):
123 cycles.append(cycle)
130 cycles = [] variable
150 def iter_cycles(cycles): argument
152 for cycle in cycles:
166 expand(path_queue, path_lens, cycles, src_map)
168 average = sum([len(x)+1 for x in cycles]) / len(cycles)
171 counted = list(iter_cycles(cycles))
181 for cycle in cycles:
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleA9.td81 // No operand cycles
468 // Extra latency cycles since wbck is 2 cycles
477 // Extra latency cycles since wbck is 2 cycles
487 // Extra latency cycles since wbck is 4 cycles
496 // Extra latency cycles since wbck is 4 cycles
880 // Extra latency cycles since wbck is 7 cycles
908 // Extra latency cycles since wbck is 7 cycles
1279 // Extra latency cycles since wbck is 6 cycles
1288 // Extra latency cycles since wbck is 6 cycles
1297 // Extra latency cycles since wbck is 6 cycles
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dearly-ifcvt-remarks.ll6 ; CHECK-SAME: and the short leg adds another {{[0-9]+}} cycles{{s?}},
7 ; CHECK-SAME: and the long leg adds another {{[0-9]+}} cycles{{s?}},
8 ; CHECK-SAME: each staying under the threshold of {{[0-9]+}} cycles{{s?}}.
23 ; CHECK-SAME: the condition would add {{[0-9]+}} cycles{{s?}} to the critical path,
24 ; CHECK-SAME: and the short leg would add another {{[0-9]+}} cycles{{s?}},
25 …ME: and the long leg would add another {{[0-9]+}} cycles{{s?}} exceeding the limit of {{[0-9]+}} c…
43 ; CHECK-SAME: the resulting critical path ({{[0-9]+}} cycles{{s?}})
45 ; CHECK-SAME: by more than the threshold of {{[0-9]+}} cycles{{s?}},
/llvm-project-15.0.7/llvm/test/Transforms/EarlyCSE/AMDGPU/
H A Dmemrealtime.ll7 define amdgpu_kernel void @memrealtime(i64 %cycles) #0 {
10 %cmp3 = icmp sgt i64 %cycles, 0
16 %cmp = icmp slt i64 %sub, %cycles
26 define amdgpu_kernel void @memtime(i64 %cycles) #0 {
29 %cmp3 = icmp sgt i64 %cycles, 0
35 %cmp = icmp slt i64 %sub, %cycles
/llvm-project-15.0.7/llvm/docs/
H A DCycleTerminology.rst30 cycles found in the CFG is the same. These are the *top-level
31 cycles* that do not themselves have a parent.
32 5. The cycles nested inside a cycle C with header H are the outermost
33 cycles in the subgraph induced on the set of nodes (C - H). C is
34 said to be the *parent* of these cycles, and each of these cycles
37 Thus, cycles form an implementation-defined forest where each cycle C is
38 the parent of any outermost cycles nested inside C. The tree closely
65 - Non-header entry blocks of a cycle can be contained in child cycles.
107 natural loops. A possible hierarchy of cycles is::
147 hierarchy of cycles is::
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX3T110.td118 // 3 cycles on I1.
124 // 4 cycles on I1.
130 // 5 cycles on I1.
136 // 7 cycles on I1.
142 // 23 cycles on I1.
149 // 39 cycles on I1.
162 // 8 cycles on I2/I3
174 // 8 cycles on I1/I2/I3
240 // 4 cycles on F2/F3.
296 // 2 cycles on LS0/LS1.
[all …]
/llvm-project-15.0.7/libc/benchmarks/
H A Dlibc-benchmark-analysis.py358 if mode == "cycles":
64 FormatterUnit = {"time":"s","cycles":"","bytespercycle":"B/cycle"}[mode]
65 Label = {"time":"Time","cycles":"Cycles","bytespercycle":"Byte/cycle"}[mode]
84 local["cycles"] = local["time"] * getCpuFrequency(study)
92 FormatterUnit = {"time":"s","cycles":""}[mode]
93 Label = {"time":"Time","cycles":"Cycles"}[mode]
104 …ment("--mode", choices=["time", "cycles", "bytespercycle"], default="time", help="Use to display e…
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/BdVer2/
H A Dstore-throughput.s89 # CHECK-NEXT: [# dispatched], [# cycles]
94 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
95 # CHECK-NEXT: [# issued], [# cycles]
319 # CHECK-NEXT: [# dispatched], [# cycles]
324 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
325 # CHECK-NEXT: [# issued], [# cycles]
549 # CHECK-NEXT: [# dispatched], [# cycles]
555 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
556 # CHECK-NEXT: [# issued], [# cycles]
781 # CHECK-NEXT: [# dispatched], [# cycles]
[all …]
H A Dload-throughput.s89 # CHECK-NEXT: [# dispatched], [# cycles]
94 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
95 # CHECK-NEXT: [# issued], [# cycles]
319 # CHECK-NEXT: [# dispatched], [# cycles]
324 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
325 # CHECK-NEXT: [# issued], [# cycles]
549 # CHECK-NEXT: [# dispatched], [# cycles]
554 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
555 # CHECK-NEXT: [# issued], [# cycles]
781 # CHECK-NEXT: [# dispatched], [# cycles]
[all …]
H A Dload-store-throughput.s81 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
82 # CHECK-NEXT: [# dispatched], [# cycles]
89 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
90 # CHECK-NEXT: [# issued], [# cycles]
317 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
318 # CHECK-NEXT: [# dispatched], [# cycles]
325 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
326 # CHECK-NEXT: [# issued], [# cycles]
554 # CHECK-NEXT: [# dispatched], [# cycles]
560 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/
H A Doption-all-stats-1.s39 # FULLREPORT: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
40 # FULLREPORT-NEXT: [# dispatched], [# cycles]
45 # FULLREPORT: Schedulers - number of cycles where we saw N micro opcodes issued:
46 # FULLREPORT-NEXT: [# issued], [# cycles]
H A Doption-all-stats-2.s40 # FULL: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
41 # FULL-NEXT: [# dispatched], [# cycles]
46 # ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
47 # ALL-NEXT: [# issued], [# cycles]
H A Doption-all-views-1.s61 # FULLREPORT: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
62 # FULLREPORT-NEXT: [# dispatched], [# cycles]
67 # FULLREPORT: Schedulers - number of cycles where we saw N micro opcodes issued:
68 # FULLREPORT-NEXT: [# issued], [# cycles]
H A Doption-all-views-2.s60 # ALL: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
61 # ALL-NEXT: [# dispatched], [# cycles]
66 # ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
67 # ALL-NEXT: [# issued], [# cycles]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Cortex/
H A DA55-all-stats.s46 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
47 # CHECK-NEXT: [# dispatched], [# cycles]
52 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
53 # CHECK-NEXT: [# issued], [# cycles]
H A DA55-all-views.s46 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
47 # CHECK-NEXT: [# dispatched], [# cycles]
52 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
53 # CHECK-NEXT: [# issued], [# cycles]
H A DA55-out-of-order-retire.s46 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
47 # CHECK-NEXT: [# dispatched], [# cycles]
51 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
52 # CHECK-NEXT: [# issued], [# cycles]
H A DA55-in-order-retire.s46 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
47 # CHECK-NEXT: [# dispatched], [# cycles]
52 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
53 # CHECK-NEXT: [# issued], [# cycles]
/llvm-project-15.0.7/llvm/cmake/modules/
H A DFindLibpfm.cmake20 # Check to see if perf_branch_entry has the field 'cycles'.
21 # We couldn't use CheckStructHasMember here because 'cycles' is a bit field which is not
27 entry.cycles = 2;
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/Barcelona/
H A Dload-store-throughput.s81 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
82 # CHECK-NEXT: [# dispatched], [# cycles]
87 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
88 # CHECK-NEXT: [# issued], [# cycles]
275 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
276 # CHECK-NEXT: [# dispatched], [# cycles]
281 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
282 # CHECK-NEXT: [# issued], [# cycles]
470 # CHECK-NEXT: [# dispatched], [# cycles]
475 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
[all …]
H A Dstore-throughput.s81 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
82 # CHECK-NEXT: [# dispatched], [# cycles]
88 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
89 # CHECK-NEXT: [# issued], [# cycles]
277 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
278 # CHECK-NEXT: [# dispatched], [# cycles]
284 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
285 # CHECK-NEXT: [# issued], [# cycles]
474 # CHECK-NEXT: [# dispatched], [# cycles]
480 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
[all …]
H A Dload-throughput.s81 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
82 # CHECK-NEXT: [# dispatched], [# cycles]
87 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
88 # CHECK-NEXT: [# issued], [# cycles]
275 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
276 # CHECK-NEXT: [# dispatched], [# cycles]
281 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
282 # CHECK-NEXT: [# issued], [# cycles]
470 # CHECK-NEXT: [# dispatched], [# cycles]
475 # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
[all …]
/llvm-project-15.0.7/third-party/benchmark/src/
H A Dcycleclock.h207 uint64_t cycles; in Now()
208 asm volatile("rdcycle %0" : "=r"(cycles)); in Now()
209 return cycles; in Now()

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