| /llvm-project-15.0.7/lldb/test/API/functionalities/postmortem/FreeBSDKernel/ |
| H A D | vmcore-amd64-minidump.bz2 | 1minidump FreeBSD/ |
| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEInstrFormats.td | 72 bits<1> cy = 1;
80 let Inst{47} = cy;
104 let cy = 0;
121 bits<1> cy = 1;
131 let Inst{47} = cy;
148 bits<1> cy = 1;
160 let Inst{47} = cy;
212 bits<1> cy = 1;
225 let Inst{47} = cy;
251 bits<1> cy = 1;
[all …]
|
| H A D | VEInstrVec.td | 149 let cy = 0 in
200 let cy = 0 in
265 let cy = 0 in
317 let cy = 0 in
361 let cy = 0 in
383 let cy = 0 in
397 let cy = 0 in
417 let cy = 0 in
434 let cy = 0 in
472 let cy = 0 in
[all …]
|
| H A D | VEInstrInfo.td | 544 let cy = 0 in
573 let cy = 0 in
624 let cy = 0 in
643 let cy = 0 in
660 let cy = 0 in
687 let cy = 0 in
704 let cy = 0 in
721 let cy = 0 in
747 let cy = 0 in
765 let cy = 0 in
[all …]
|
| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | clang-sections-tentative.c | 24 const int cy; // not assigned a section attribute variable
29 const int cy; // .rodata.2 variable
|
| /llvm-project-15.0.7/clang/test/SemaCXX/ |
| H A D | cxx17-compat.cpp | 77 static auto [cx, cy, cz] = C();
84 static thread_local auto [cx, cy, cz] = C(); in f()
|
| H A D | warn-unused-filescoped.cpp | 85 const unsigned int cy = 0; variable
86 int f5() { return cy; } in f5()
|
| /llvm-project-15.0.7/libcxx/test/std/utilities/utility/forward/ |
| H A D | move.pass.cpp | 53 const int cy = y; in test_constexpr_move() local
55 && std::move(cy) == 42 in test_constexpr_move()
|
| /llvm-project-15.0.7/polly/test/CodeGen/ |
| H A D | invariant_loads_from_struct_with_different_types_2.ll | 36 …%cy = getelementptr inbounds %struct.FFIIRFilterCoeffs.0.3.6.63.78.81.87.102.150.162.165.168.171, …
37 %0 = load float*, float** %cy, align 4
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ScheduleBtVer2.td | 181 // Instructions that have local forwarding disabled have an extra +1cy latency.
185 // benefit from STLF, and their observed latency is 6cy. That is the reason why
186 // this write adds two extra cycles (instead of just 1cy for the store).
429 // XADD %ecx, (%rsp) ## Instruction latency: 11cy
430 // ## ECX write Latency: 3cy
434 // latency is assumed to be 3cy.
447 // LOCK XADD %ecx, (%rsp) ## Instruction Latency: 16cy
448 // ## ECX write Latency: 11cy
450 // The value of ECX becomes available only after 11cy from the start of
462 // the output register operand becomes visible after 11cy. However, we want to
[all …]
|
| /llvm-project-15.0.7/clang/test/Index/Core/ |
| H A D | index-subkinds.m | 30 // CHECK-NEXT: RelExt,RelCont | cat | c:objc(cy)MyTestCase@cat
31 // CHECK: [[@LINE+1]]:23 | extension(test)/ObjC | cat | c:objc(cy)MyTestCase@cat | <no-cgname> | De…
35 // CHECK: [[@LINE+1]]:28 | extension(test)/ObjC | cat | c:objc(cy)MyTestCase@cat | <no-cgname> | De…
|
| H A D | external-source-symbol-attr.m | 42 // CHECK: [[@LINE-1]]:15 | extension/ObjC | cat | c:@M@some_module@objc(cy)I1@cat |
49 // CHECK: [[@LINE-1]]:15 | extension/Swift | cat2 | c:@CM@cat_module@some_module@objc(cy)I1@cat2 |
|
| H A D | index-source.m | 223 // CHECK-NEXT: RelExt,RelCont | bar | c:objc(cy)I3@bar
224 // CHECK: [[@LINE+3]]:15 | extension/ObjC | bar | c:objc(cy)I3@bar | <no-cgname> | Decl | rel: 0
226 // CHECK-NEXT: RelBase,RelCont | bar | c:objc(cy)I3@bar
231 // CHECK: [[@LINE+1]]:20 | extension/ObjC | bar | c:objc(cy)I3@bar | <no-cgname> | Def | rel: 0
|
| /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/ |
| H A D | int-cmp-02.ll | 48 ; CHECK: cy %r2, 4096(%r3)
62 ; CHECK: cy %r2, 524284(%r3)
92 ; CHECK: cy %r2, -4(%r3)
106 ; CHECK: cy %r2, -524288(%r3)
152 ; CHECK: cy %r2, 4096({{%r4,%r3|%r3,%r4}})
|
| /llvm-project-15.0.7/llvm/lib/Target/VE/Disassembler/ |
| H A D | VEDisassembler.cpp | 319 bool cy = fieldFromInstruction(insn, 47, 1); in DecodeASX() local
335 if (cy) { in DecodeASX()
470 bool cy = fieldFromInstruction(insn, 47, 1); in DecodeCAS() local
485 if (cy && !isImmOnly) { in DecodeCAS()
602 bool cy = fieldFromInstruction(insn, 47, 1); in DecodeBranchCondition() local
610 if (cy) { in DecodeBranchCondition()
|
| /llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/BdVer2/ |
| H A D | read-advance-1.s | 4 # The vmul can start executing 3cy in advance. That is beause the first use
|
| H A D | rcu-statistics.s | 66 # CHECK-NEXT: Average Used ROB Entries per cy: 9 ( 7.0% )
|
| H A D | zero-idioms-avx-256.s | 5 # Those vector XOR instructions should only consume 1cy of JFPU1 (instead
6 # of 2cy).
|
| /llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/Barcelona/ |
| H A D | read-advance-1.s | 4 # The vmul can start executing 2cy in advance. That is beause the first use
|
| H A D | rcu-statistics.s | 64 # CHECK-NEXT: Average Used ROB Entries per cy: 9 ( 5.4% )
|
| /llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/BtVer2/ |
| H A D | read-advance-1.s | 4 # The vmul can start executing 3cy in advance. That is beause the first use
|
| H A D | rcu-statistics.s | 64 # CHECK-NEXT: Average Used ROB Entries per cy: 11 ( 17.2% )
|
| H A D | zero-idioms-avx-256.s | 5 # Those vector XOR instructions should only consume 1cy of JFPU1 (instead
6 # of 2cy).
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | stack-tagging.ll | 164 %cy = bitcast i32* %y to i8*
168 %cxcy = select i1 %tobool, i8* %cx, i8* %cy
|
| /llvm-project-15.0.7/llvm/test/Instrumentation/MemorySanitizer/ |
| H A D | alloca.ll | 154 %cy = bitcast i32* %y to i8*
158 %cxcy = select i1 %tobool, i8* %cx, i8* %cy
|