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/llvm-project-15.0.7/llvm/test/MC/Sparc/
H A Dsparc-coproc.s51 ! CHECK: ld [%i5], %csr ! encoding: [0xc1,0x8f,0x40,0x00]
52 ! CHECK: ld [%l2+3], %csr ! encoding: [0xc1,0x8c,0xa0,0x03]
53 ! CHECK: ld [%l4+%l5], %csr ! encoding: [0xc1,0x8d,0x00,0x15]
54 ld [%i5], %csr
55 ld [%l2+3], %csr
56 ld [%l4+%l5], %csr
59 ! CHECK: st %csr, [%i2] ! encoding: [0xc1,0xae,0x80,0x00]
60 ! CHECK: st %csr, [%i2+31] ! encoding: [0xc1,0xae,0xa0,0x1f]
62 st %csr, [%i2]
63 st %csr, [%i2+31]
[all …]
/llvm-project-15.0.7/mlir/test/Integration/Dialect/SparseTensor/taco/
H A Dtest_SpMM.py16 csr = pt.format([pt.dense, pt.compressed], [0, 1]) variable
19 A = pt.read(os.path.join(_SCRIPT_PATH, "data/A.mtx"), csr)
20 B = pt.read(os.path.join(_SCRIPT_PATH, "data/B.mtx"), csr)
21 C = pt.tensor([A.shape[0], B.shape[1]], csr)
H A Dtest_SpMV.py21 csr = pt.format([dense, compressed]) variable
30 A = pt.read(os.path.join(_SCRIPT_PATH, "data/pwtk.mtx"), csr)
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Darg-copy-elide.ll33 ; CHECK: push {[[csr:[^ ]*]], lr}
35 ; CHECK: ldr [[csr]], [sp, #8]
37 ; CHECK: mov r0, [[csr]]
38 ; CHECK: pop {[[csr]], pc}
/llvm-project-15.0.7/flang/include/flang/Parser/
H A Dmessage.h197 Message(CharBlock csr, const MessageFixedText &t) in Message() argument
198 : location_{csr}, text_{t} {} in Message()
199 Message(CharBlock csr, const MessageFormattedText &s) in Message() argument
200 : location_{csr}, text_{s} {} in Message()
201 Message(CharBlock csr, MessageFormattedText &&s) in Message() argument
202 : location_{csr}, text_{std::move(s)} {} in Message()
203 Message(CharBlock csr, const MessageExpectedText &t) in Message() argument
204 : location_{csr}, text_{t} {} in Message()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dipra-regmask.ll4 ; CHECK-DAG: csr Clobbered Registers: $vgpr0 $vgpr0_hi16 $vgpr0_lo16 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4…
5 define void @csr() #0 {
39 @llvm.used = appending global [6 x i8*] [i8* bitcast (void ()* @csr to i8*),
H A Dneed-fp-from-vgpr-spills.ll48 ; CHECK-NEXT: ; clobber csr v40
62 call void asm sideeffect "; clobber csr v40", "~{v40}"()
99 ; CHECK-NEXT: ; clobber csr v40
111 call void asm sideeffect "; clobber csr v40", "~{v40}"()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td936 def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, csr_sysreg:$csr, X0)>;
937 def : InstAlias<"csrw $csr, $rs", (CSRRW X0, csr_sysreg:$csr, GPR:$rs)>;
938 def : InstAlias<"csrs $csr, $rs", (CSRRS X0, csr_sysreg:$csr, GPR:$rs)>;
939 def : InstAlias<"csrc $csr, $rs", (CSRRC X0, csr_sysreg:$csr, GPR:$rs)>;
941 def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>;
942 def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>;
943 def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>;
946 def : InstAlias<"csrw $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>;
947 def : InstAlias<"csrs $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>;
948 def : InstAlias<"csrc $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>;
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcfi-inserter-verify-inconsistent-csr.mir3 # Test that CFI verifier finds inconsistent csr saved set between bb.end and
H A Dstatepoint-fixup-call.mir2 # RUN: llc -o - %s -fixup-allow-gcptr-in-csr=false -run-pass fixup-statepoint-caller-saved | FileCh…
H A Dstatepoint-vreg.mir2 # RUN: llc -o - %s -fixup-allow-gcptr-in-csr=true -start-after=finalize-isel | FileCheck %s
H A Dstatepoint-fixup-invoke.mir2 # RUN: llc -o - %s -fixup-allow-gcptr-in-csr=false -run-pass fixup-statepoint-caller-saved | FileCh…
H A Dstatepoint-fixup-shared-ehpad.mir2 # RUN: llc -o - %s -fixup-allow-gcptr-in-csr=false -run-pass fixup-statepoint-caller-saved | FileCh…
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dreverse-csr-restore-seq.mir1 # RUN: llc -run-pass=prologepilog -reverse-csr-restore-seq -o - -mtriple=aarch64-- %s | FileCheck %…
2 # RUN: llc -start-before=prologepilog -stop-after=aarch64-ldst-opt -reverse-csr-restore-seq -o - -m…
H A Dragreedy-csr.ll1 ; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -regalloc=greedy -regalloc-csr-first-time-cost=15 | Fil…
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Sparc/
H A Dsparc-special-registers.txt39 # CHECK: st %csr, [%i5]
/llvm-project-15.0.7/lld/test/MachO/
H A Ddependency-info.s7 # RUN: llvm-ar csr %t/bar.a %t/bar.o
H A Dt.s8 # RUN: llvm-ar csr %t/bar.a %t/bar.o
H A Du.s5 # RUN: llvm-ar csr %t/lib.a %t/foo.o
H A Dthin-archive.s8 # RUN: llvm-ar csr %t/lib.a %t/lib.o
H A Dwhy-load.s7 # RUN: llvm-ar csr %t/lib.a %t/objc.o %t/foo.o %t/bar.o
/llvm-project-15.0.7/llvm/test/CodeGen/Lanai/
H A Dpeephole-compare.mir648 CALL @g, csr, implicit-def dead $rca, implicit $sp, implicit-def $sp, implicit-def $rv
667 CALL @g, csr, implicit-def dead $rca, implicit $sp, implicit-def $sp, implicit-def $rv
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Duser-csr-names.s135 # Tests in rvf-user-mode-csr.s
H A Drv32i-invalid.s86 ## named csr in place of uimm12
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.td595 "ld [$addr], %csr", []>;
597 "ld [$addr], %csr", []>;
660 "st %csr, [$addr]", [], IIC_st>;
662 "st %csr, [$addr]", [], IIC_st>;

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