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Searched refs:csinc (Results 1 – 25 of 39) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Daarch64-isel-csinc.ll4 ; Verify that we can fold csneg/csel into csinc instruction.
15 ; CHECK-NEXT: csinc w0, w8, w1, eq
30 ; CHECK-NEXT: csinc w0, w8, w1, ne
45 ; CHECK-NEXT: csinc w0, w8, w1, ne
60 ; CHECK-NEXT: csinc w0, w8, w1, eq
75 ; CHECK-NEXT: csinc w0, w8, w1, eq
90 ; CHECK-NEXT: csinc w0, w8, w1, eq
99 ; prevent larger constants (the add laid after csinc)
106 ; CHECK-NEXT: csinc w8, w8, wzr, eq
122 ; CHECK-NEXT: csinc w0, w8, w1, ne
[all …]
H A Daarch64-isel-csinc-type.ll4 ; Verify that we can fold csneg/csel into csinc instruction.
15 ; CHECK-NEXT: csinc w0, w8, w1, ne
30 ; CHECK-NEXT: csinc w0, w8, w1, ne
45 ; CHECK-NEXT: csinc w0, w8, w1, ne
60 ; CHECK-NEXT: csinc x0, x8, x1, ne
75 ; CHECK-NEXT: csinc x0, x8, x1, ne
90 ; CHECK-NEXT: csinc x0, x8, x1, eq
H A Duse-cr-result-of-dom-icmp-st.ll22 ; CHECK-NEXT: csinc x8, x1, xzr, eq
46 ; CHECK-NEXT: csinc x9, x1, xzr, eq
71 ; CHECK-NEXT: csinc x8, x1, xzr, eq
95 ; CHECK-NEXT: csinc x8, x1, xzr, eq
119 ; CHECK-NEXT: csinc x8, x1, xzr, eq
142 ; CHECK-NEXT: csinc x8, x1, xzr, eq
164 ; CHECK-NEXT: csinc x8, x1, xzr, eq
187 ; CHECK-NEXT: csinc x8, x1, xzr, eq
209 ; CHECK-NEXT: csinc x8, x1, xzr, eq
231 ; CHECK-NEXT: csinc x8, x1, xzr, eq
[all …]
H A Dcond-sel-value-prop.ll65 ; CHECK-NEXT: csinc x0, x8, xzr, ne
91 ; CHECK-NEXT: csinc x0, x0, xzr, eq
102 ; CHECK-NEXT: csinc x0, x0, xzr, eq
H A Dvector-op-scalarize-strict.ll35 ; CHECK-NEXT: csinc w0, w8, wzr, vc
47 ; CHECK-NEXT: csinc w0, w8, wzr, vc
H A Dcond-sel.ll67 ; CHECK: csinc {{w[0-9]+}}, [[LHS]], [[RHS]], ls
75 ; CHECK: csinc {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
84 ; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
92 ; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
209 ; N.b. code is not optimal here (32-bit csinc would be better) but
H A Darm64-csel.ll84 ; CHECK-NEXT: csinc w0, w8, wzr, le
285 ; CHECK-NEXT: csinc w0, w8, wzr, eq
297 ; CHECK-NEXT: csinc x0, x8, xzr, eq
309 ; CHECK-NEXT: csinc w0, w8, wzr, ne
321 ; CHECK-NEXT: csinc x0, x8, xzr, ne
H A Darm64-fast-isel-fcmp.ll87 ; CHECK-NEXT: csinc {{w[0-9]+}}, [[REG]], wzr, le
112 ; CHECK-NEXT: csinc {{w[0-9]+}}, [[REG]], wzr, vc
H A Difcvt-select.ll7 ;CHECK: csinc
H A Darm64-early-ifcvt.ll42 ; CHECK-NEXT: csinc w0, w1, w0, eq
60 ; CHECK-NEXT: csinc x0, x1, x0, eq
78 ; CHECK-NEXT: csinc w0, w1, w0, ne
96 ; CHECK-NEXT: csinc x0, x1, x0, ne
H A Dbranch-relax-bcc.ll53 ; CHECK-NEXT: csinc w8, w8, w1, lt
H A Dfptoui-sat-scalar.ll25 ; CHECK-NEXT: csinc w0, w8, wzr, lo
174 ; CHECK-NEXT: csinc w0, w8, wzr, lo
324 ; CHECK-CVT-NEXT: csinc w0, w8, wzr, lo
331 ; CHECK-FP16-NEXT: csinc w0, w8, wzr, lo
H A Dfpclamptosat_vec.ll410 ; CHECK-NEXT: csinc x9, x1, xzr, lt
413 ; CHECK-NEXT: csinc x11, x20, xzr, lt
523 ; CHECK-NEXT: csinc x8, x1, xzr, lt
527 ; CHECK-NEXT: csinc x11, x20, xzr, lt
649 ; CHECK-NEXT: csinc x8, x1, xzr, lt
653 ; CHECK-NEXT: csinc x11, x20, xzr, lt
1062 ; CHECK-NEXT: csinc x9, x1, xzr, lt
1066 ; CHECK-NEXT: csinc x11, x20, xzr, lt
1169 ; CHECK-NEXT: csinc x9, x1, xzr, lt
1173 ; CHECK-NEXT: csinc x11, x20, xzr, lt
[all …]
H A Dhalf.ll113 ; CHECK-NEXT: csinc w8, w8, wzr, mi
H A Dfp-intrinsics-fp16.ll744 ; CHECK-NOFP16-NEXT: csinc w0, w8, wzr, le
751 ; CHECK-FP16-NEXT: csinc w0, w8, wzr, le
841 ; CHECK-NOFP16-NEXT: csinc w0, w8, wzr, vc
848 ; CHECK-FP16-NEXT: csinc w0, w8, wzr, vc
976 ; CHECK-NOFP16-NEXT: csinc w0, w8, wzr, le
983 ; CHECK-FP16-NEXT: csinc w0, w8, wzr, le
1073 ; CHECK-NOFP16-NEXT: csinc w0, w8, wzr, vc
1080 ; CHECK-FP16-NEXT: csinc w0, w8, wzr, vc
H A Dfpclamptosat.ll400 ; CHECK-NEXT: csinc x9, x1, xzr, lt
463 ; CHECK-NEXT: csinc x9, x1, xzr, lt
532 ; CHECK-NEXT: csinc x9, x1, xzr, lt
922 ; CHECK-NEXT: csinc x9, x1, xzr, lt
979 ; CHECK-NEXT: csinc x9, x1, xzr, lt
1042 ; CHECK-NEXT: csinc x9, x1, xzr, lt
H A Dcall-rv-marker.ll52 ; GISEL: csinc w0, w8, wzr, eq
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dthumbv8.1m.s1068 csinc lr, r2, r2, hs label
1100 # CHECK: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e]
1101 # CHECK-FP: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e]
1102 # CHECK-NOLOB: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e]
1103 csinc lr, r10, r7, le label
1131 csinc r0, sp, r1, eq label
1133 csinc r0, pc, r1, eq label
1156 csinc r0, r0, r1, ne label
H A Dmve-scalar-shift.s52 csinc lr, r2, r2, hs label
78 # CHECK: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e]
79 # CHECK-NOMVE: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e]
80 csinc lr, r10, r7, le label
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dfold-select.mir70 name: csinc
79 ; CHECK-LABEL: name: csinc
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dthumbv8.1m.s26 # CHECK: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Neoverse/
H A DN2-basic-instructions.s390 csinc w1, w0, w19, ne label
391 csinc wzr, w5, w9, eq label
392 csinc w9, wzr, w30, gt label
393 csinc w1, w28, wzr, mi label
394 csinc x19, x23, x29, lt label
395 csinc xzr, x3, x4, ge label
396 csinc x5, xzr, x6, hs label
397 csinc x7, x8, xzr, lo label
418 csinc w2, wzr, wzr, al label
426 csinc w5, w6, w6, nv label
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Cortex/
H A DA55-basic-instructions.s390 csinc w1, w0, w19, ne label
391 csinc wzr, w5, w9, eq label
392 csinc w9, wzr, w30, gt label
393 csinc w1, w28, wzr, mi label
394 csinc x19, x23, x29, lt label
395 csinc xzr, x3, x4, ge label
396 csinc x5, xzr, x6, hs label
397 csinc x7, x8, xzr, lo label
418 csinc w2, wzr, wzr, al label
426 csinc w5, w6, w6, nv label
[all …]
/llvm-project-15.0.7/clang/test/Driver/
H A Darmv8.1m.main.s31 csinc r0, r1, r2, eq label
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dcsel.ll122 ; CHECK-NEXT: csinc r0, r1, r2, gt
135 ; CHECK-NEXT: csinc r0, r2, r1, le

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