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/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Ddirective-arch_extension-crc.s10 .arch_extension crc
12 @ CHECK-V7-NEXT: .arch_extension crc
15 .type crc,%function
16 crc: label
18 @ CHECK-V7: error: instruction requires: crc armv8
40 @ CHECK-V8: error: instruction requires: crc
43 @ CHECK-V8: error: instruction requires: crc
46 @ CHECK-V8: error: instruction requires: crc
50 @ CHECK-V8: error: instruction requires: crc
53 @ CHECK-V8: error: instruction requires: crc
[all …]
H A Dcrc32.s11 @ CHECK-V7: error: instruction requires: crc armv8
12 @ CHECK-V7: error: instruction requires: crc armv8
13 @ CHECK-V7: error: instruction requires: crc armv8
14 @ CHECK-NOCRC: error: instruction requires: crc
15 @ CHECK-NOCRC: error: instruction requires: crc
16 @ CHECK-NOCRC: error: instruction requires: crc
25 @ CHECK-V7: error: instruction requires: crc armv8
26 @ CHECK-V7: error: instruction requires: crc armv8
28 @ CHECK-NOCRC: error: instruction requires: crc
29 @ CHECK-NOCRC: error: instruction requires: crc
[all …]
H A Dcrc32-thumb.s11 @ CHECK-V7: error: instruction requires: crc armv8
12 @ CHECK-V7: error: instruction requires: crc armv8
13 @ CHECK-V7: error: instruction requires: crc armv8
14 @ CHECK-NOCRC: error: instruction requires: crc
15 @ CHECK-NOCRC: error: instruction requires: crc
16 @ CHECK-NOCRC: error: instruction requires: crc
25 @ CHECK-V7: error: instruction requires: crc armv8
26 @ CHECK-V7: error: instruction requires: crc armv8
28 @ CHECK-NOCRC: error: instruction requires: crc
29 @ CHECK-NOCRC: error: instruction requires: crc
[all …]
/llvm-project-15.0.7/lld/test/COFF/
H A Dpdb-publics-import.test29 CHECK-NEXT: SC[.text] | mod = 0, 0001:0000, size = 8, data crc = 0, reloc crc = 0
36 CHECK-NEXT: SC[???] | mod = 65535, 65535:0000, size = -1, data crc = 0, reloc crc = 0
42 CHECK-NEXT: SC[.text] | mod = 2, 0001:0032, size = 6, data crc = 0, reloc crc = 0
48 CHECK-NEXT: SC[???] | mod = 65535, 65535:0000, size = -1, data crc = 0, reloc crc = 0
151 CHECK-NEXT: SC[.text] | mod = 0, 0001:0000, size = 8, data crc = 0, reloc crc = 0
155 CHECK-NEXT: SC[.text] | mod = 3, 0001:0016, size = 6, data crc = 0, reloc crc = 0
158 CHECK-NEXT: SC[.text] | mod = 3, 0001:0032, size = 6, data crc = 0, reloc crc = 0
169 CHECK-NEXT: SC[.rdata] | mod = 3, 0002:0104, size = 8, data crc = 0, reloc crc = 0
171 CHECK-NEXT: SC[.rdata] | mod = 3, 0002:0112, size = 8, data crc = 0, reloc crc = 0
173 CHECK-NEXT: SC[.rdata] | mod = 3, 0002:0120, size = 8, data crc = 0, reloc crc = 0
[all …]
H A Dpdb.test123 RAW-NEXT: SC[.text] | mod = 0, 0001:0000, size = 14, data crc = 1682752513, reloc crc…
130 RAW-NEXT: SC[.text] | mod = 1, 0001:0016, size = 6, data crc = 2139436471, reloc crc …
137 RAW-NEXT: SC[???] | mod = 65535, 65535:0000, size = -1, data crc = 0, reloc crc = 0
254 RAW-NEXT: SC[.text] | mod = 0, 0001:0000, size = 14, data crc = 1682752513, reloc crc = 0
257 RAW-NEXT: SC[.text] | mod = 1, 0001:0016, size = 6, data crc = 2139436471, reloc crc = 0
260 RAW-NEXT: SC[.rdata] | mod = 2, 0002:0000, size = {{[0-9]+}}, data crc = 0, reloc crc = 0
262 RAW-NEXT: SC[.rdata] | mod = 2, 0002:0028, size = {{[0-9]+}}, data crc = 0, reloc crc = 0
264 RAW-NEXT: SC[.rdata] | mod = 0, 0002:0064, size = {{[0-9]+}}, data crc = 264583633, reloc crc = 0
266 RAW-NEXT: SC[.pdata] | mod = 0, 0003:0000, size = 12, data crc = 361370162, reloc crc = 0
H A Dpdb-natvis.test17 CHECK-FIRST: {{.*}}natvis-1.natvis (16 bytes): obj=<null>, vname={{.*}}natvis-1.natvis, crc=35…
20 CHECK-SECOND: {{.*}}natvis-2.natvis (19 bytes): obj=<null>, vname={{.*}}natvis-2.natvis, crc=4…
23 CHECK-THIRD: {{.*}}natvis-3.natvis (18 bytes): obj=<null>, vname={{.*}}natvis-3.natvis, crc=20…
/llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Integer/
H A Dcrc.s8 # CHECK-ASM-AND-OBJ: crc.w.b.w $s1, $a3, $tp
10 crc.w.b.w $s1, $a3, $tp
12 # CHECK-ASM-AND-OBJ: crc.w.h.w $s8, $a6, $t6
14 crc.w.h.w $s8, $a6, $t6
16 # CHECK-ASM-AND-OBJ: crc.w.w.w $s5, $a2, $a6
18 crc.w.w.w $s5, $a2, $a6
20 # CHECK-ASM-AND-OBJ: crc.w.d.w $s5, $a7, $s8
22 crc.w.d.w $s5, $a7, $s8
/llvm-project-15.0.7/llvm/unittests/Support/
H A DCRCTest.cpp33 uint32_t crc = i; in TEST() local
35 uint32_t mask = -(crc & 1); in TEST()
36 crc = (crc >> 1) ^ (0xEDB88320 & mask); in TEST()
41 EXPECT_EQ(crc, ~llvm::crc32(0xFFFFFFFFU, byte)); in TEST()
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dclr_set_toggle.ll70 define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind {
74 %crc.addr = alloca i16, align 2
75 store i16 %crc, i16* %crc.addr, align 2
76 %0 = load i16, i16* %crc.addr, align 2
80 store i16 %conv1, i16* %crc.addr, align 2
81 %1 = load i16, i16* %crc.addr, align 2
133 %crc.addr = alloca i16, align 2
134 store i16 %crc, i16* %crc.addr, align 2
135 %0 = load i16, i16* %crc.addr, align 2
139 store i16 %conv1, i16* %crc.addr, align 2
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dase_warnings.ll41 ; Check crc warnings.
42 ; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+crc < %s 2>&1 | \
44 ; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+crc < %s 2>&1 | \
46 ; RUN: llc -march=mips -mattr=+mips32r6 -mattr=+crc < %s 2>&1 | \
48 ; RUN: llc -march=mips64 -mattr=+mips64r6 -mattr=+crc < %s 2>&1 | \
81 ; CRC_32: warning: the 'crc' ASE requires MIPS32 revision 6 or greater
82 ; CRC_64: warning: the 'crc' ASE requires MIPS64 revision 6 or greater
83 ; CRC_32_NO_WARNING-NOT: warning: the 'crc' ASE requires MIPS32 revision 6 or greater
84 ; CRC_64_NO_WARNING-NOT: warning: the 'crc' ASE requires MIPS64 revision 6 or greater
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfunction-subtarget-features.ll57 define i32 @bar(i32 %crc, ptr %a) #3 {
59 %crc.addr = alloca i32, align 4
61 store i32 %crc, ptr %crc.addr, align 4
63 %0 = load i32, ptr %crc.addr, align 4
/llvm-project-15.0.7/lld/tools/lld/
H A Dlld.cpp186 llvm::CrashRecoveryContext crc; in safeLldMain() local
187 if (!crc.RunSafely([&]() { in safeLldMain()
190 return {crc.RetCode, /*canRunAgain=*/false}; in safeLldMain()
195 llvm::CrashRecoveryContext crc; in safeLldMain() local
196 if (!crc.RunSafely([&]() { CommonLinkerContext::destroy(); })) { in safeLldMain()
/llvm-project-15.0.7/llvm/test/Transforms/Inline/AArch64/
H A Dinline-target-attr.ll38 attributes #0 = { "target-cpu"="generic" "target-features"="+crc,+neon" }
39 attributes #1 = { "target-cpu"="generic" "target-features"="+crc,+neon,+crypto" }
40 attributes #2 = { "target-cpu"="generic" "target-features"="+crc,+neon,+strict-align" }
/llvm-project-15.0.7/llvm/test/tools/llvm-pdbutil/
H A Dinjected-sources.test9 ; CHECK: c.natvis (140 bytes): obj=<null>, vname=c.natvis, crc=334478030, compression=None
13 ; CHECK: a.natvis (140 bytes): obj=<null>, vname=a.natvis, crc=334478030, compression=None
17 ; CHECK: b.natvis (294 bytes): obj=<null>, vname=b.natvis, crc=2059731902, compression=None
36 ; HASH: C:\src\llvm-mono\Hello.cs (92 bytes): obj=<null>, vname=c:\src\llvm-mono\hello.cs, crc…
48 …vm-mono\Hello.cs (232 bytes): obj=<null>, vname=c:\src\llvm-mono\hello.cs, crc=323787205, compress…
65 …vm-mono\Hello.cs (218 bytes): obj=<null>, vname=c:\src\llvm-mono\hello.cs, crc=616104201, compress…
H A Dinjected-sources-native.test10 ; CHECK: c.natvis (140 bytes): obj=<null>, vname=c.natvis, crc=334478030, compression=None
14 ; CHECK: a.natvis (140 bytes): obj=<null>, vname=a.natvis, crc=334478030, compression=None
18 ; CHECK: b.natvis (294 bytes): obj=<null>, vname=b.natvis, crc=2059731902, compression=None
37 ; HASH: C:\src\llvm-mono\Hello.cs (92 bytes): obj=<null>, vname=c:\src\llvm-mono\hello.cs, crc…
49 …vm-mono\Hello.cs (232 bytes): obj=<null>, vname=c:\src\llvm-mono\hello.cs, crc=323787205, compress…
66 …vm-mono\Hello.cs (218 bytes): obj=<null>, vname=c:\src\llvm-mono\hello.cs, crc=616104201, compress…
/llvm-project-15.0.7/llvm/test/CodeGen/XCore/
H A Dmisc-intrinsics.ll19 define i32 @crc32(i32 %crc, i32 %data, i32 %poly) {
22 %result = call i32 @llvm.xcore.crc32(i32 %crc, i32 %data, i32 %poly)
26 define %0 @crc8(i32 %crc, i32 %data, i32 %poly) {
29 %result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly)
/llvm-project-15.0.7/llvm/test/MC/Mips/crc/
H A Dset-nocrc-directive.s2 # RUN: -mcpu=mips32r6 -mattr=+crc 2>%t1
5 # RUN: -mcpu=mips64r6 -mattr=+crc 2>%t1
H A Dvalid.s2 # RUN: -mcpu=mips32r6 -mattr=+crc | FileCheck %s
4 # RUN: -mcpu=mips64r6 -mattr=+crc | FileCheck %s
H A Dmodule-crc.s9 # CHECK-ASM: .module crc
17 .module crc
H A Dmodule-nocrc.s1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+crc | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -filetype=obj -o - -mattr=+crc | \
H A Dinvalid.s3 # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+crc 2>%t1
5 # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 -mattr=+crc 2>%t1
65 crc $1, $2, $2 # CHECK: :[[@LINE]]:3: error: unknown instruction
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dand-elim.ll12 define zeroext i16 @test2(i16 zeroext %crc) {
14 %tmp.1 = lshr i16 %crc, 1
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Ddirective-arch-negative.s41 .arch armv8+crc
50 # CHECK: error: instruction requires: crc
/llvm-project-15.0.7/llvm/test/tools/llvm-objcopy/COFF/
H A Dadd-gnu-debuglink.test36 # Note: The last 4 bytes here are the crc of the referenced file - if the
37 # yaml2obj generated file changes, this crc changes.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Drelax-per-target-feature.ll31 …tures"="+crypto,+fp-armv8,+neon,+soft-float-abi,+strict-align,+thumb-mode,-crc,-dotprod,-dsp,-hwdi…
33 …lse" "target-cpu"="arm7tdmi" "target-features"="+strict-align,+thumb-mode,-crc,-dotprod,-dsp,-hwdi…

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