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Searched refs:covers (Results 1 – 25 of 137) sorted by relevance

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/llvm-project-15.0.7/flang/lib/Parser/
H A Dprovenance.cpp204 CHECK(origin_.back().covers.ImmediatelyPrecedes(covers)); in AddIncludedFile()
206 return covers; in AddIncludedFile()
213 CHECK(origin_.back().covers.ImmediatelyPrecedes(covers)); in AddMacroCall()
215 return covers; in AddMacroCall()
221 CHECK(origin_.back().covers.ImmediatelyPrecedes(covers)); in AddCompilerInsertion()
222 origin_.emplace_back(covers, text); in AddCompilerInsertion()
223 return covers; in AddCompilerInsertion()
321 return origin.covers.Contains(range) in GetSource()
348 return origin.covers; in GetFirstFileProvenance()
386 origin.covers.size() - origin.covers.MemberOffset(range.start())}; in IntersectionWithSourceFiles()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegisterBank.cpp37 if (!covers(RC)) in verify()
55 assert(covers(SubRC) && "Not all subclasses are covered"); in verify()
61 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers() function in RegisterBank
107 if (covers(RC)) in print()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp146 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
148 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
150 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
152 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
154 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
156 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
158 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnoip_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
160 assert(RBGPR.covers(*TRI.getRegClass( in ARMRegisterBankInfo()
163 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMSA.txt18 It is not possible to emit bclri.b since andi.b covers exactly the
24 constant since shf.w covers exactly the same cases. shf.w is used
36 It is not possible to emit ilvl.d, or pckev.d since ilvev.d covers the
40 It is not possible to emit ilvr.d, or pckod.d since ilvod.d covers the
48 It is not possible to emit splati.w since shf.w covers the same cases.
/llvm-project-15.0.7/polly/lib/External/isl/
H A Disl_bound.c303 isl_bool covers; in isl_pw_qpolynomial_fold_bound() local
344 covers = isl_pw_qpolynomial_fold_covers(bound.pwf_tight, bound.pwf); in isl_pw_qpolynomial_fold_bound()
345 if (covers < 0) in isl_pw_qpolynomial_fold_bound()
349 *tight = covers; in isl_pw_qpolynomial_fold_bound()
354 if (covers) { in isl_pw_qpolynomial_fold_bound()
H A Disl_bernstein.c377 isl_bool covers; in bernstein_coefficients_base() local
409 covers = isl_pw_qpolynomial_fold_covers(data->pwf_tight, data->pwf); in bernstein_coefficients_base()
410 if (covers < 0) in bernstein_coefficients_base()
414 *tight = covers; in bernstein_coefficients_base()
416 if (covers) { in bernstein_coefficients_base()
H A Disl_fold.c1505 int covers; in qpolynomial_fold_covers_on_domain() local
1516 covers = fold1->type == isl_fold_max ? 1 : -1; in qpolynomial_fold_covers_on_domain()
1528 if (sgn == covers) in qpolynomial_fold_covers_on_domain()
1571 isl_bool covers; in isl_pw_qpolynomial_fold_covers() local
1582 covers = qpolynomial_fold_covers_on_domain(common, in isl_pw_qpolynomial_fold_covers()
1585 if (covers < 0 || !covers) in isl_pw_qpolynomial_fold_covers()
1586 return covers; in isl_pw_qpolynomial_fold_covers()
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/
H A DREADME3 covers all features available in machine IR.
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRegisterBank.h71 bool covers(const TargetRegisterClass &RC) const;
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/readability/
H A Dsimplify-subscript-expr.rst6 This check simplifies subscript expressions. Currently this covers calling
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Daarch64-dup-ext-vectortype-crash.ll3 ; This test covers a case where extended value types can't be converted to
H A Dpatchable-function-entry-empty.mir3 ## The initial .loc covers PATCHABLE_FUNCTION_ENTER.
/llvm-project-15.0.7/compiler-rt/test/fuzzer/
H A Dset_cover_merge.test47 # it covers more features than any other file.
69 # T3/a covers almost all of the available features.
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/
H A Davoid-non-const-global-variables.rst7 …/blob/master/CppCoreGuidelines.md#Rr-global>`_ is a duplicate of rule I.2 it also covers that rule.
/llvm-project-15.0.7/clang/test/Analysis/
H A Dsolver-sym-simplification-ptr-bool.cl5 // This test case covers an issue found in the static analyzer
/llvm-project-15.0.7/llvm/test/DebugInfo/
H A Dsymbolize-split-dwarf-no-skel-address.test20 that a lack of ranges on the CU means the CU covers no addresses.
H A Dsymbolize-filter-markup-data.test18 ERR: error: no mmap covers address
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparc.td148 // - covers all the erratum fixes for LEON3, but does not support the CASA instruction.
153 // - covers all the erratum fixed for LEON3 and support for the CASA instruction.
/llvm-project-15.0.7/llvm/test/Transforms/GlobalOpt/
H A Dstore-struct-element.ll25 ; Check that we don't miscompile when the store covers the whole struct.
/llvm-project-15.0.7/llvm/test/Transforms/FunctionAttrs/
H A Dout-of-bounds-iterator-bug.ll5 ; FunctionAttrs, and in the process covers corner cases with varargs.
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Drnsbg-01.ll92 ; Test a case with a left shift and OR, where the OR covers all shifted bits.
141 ; Test a case with a right shift and OR, where the OR covers all the shifted
245 ; Test a case with a shift, OR, and rotate where the OR covers all shifted bits.
H A Dpatchpoint-invoke.ll42 ; Verify that the unwind data covers the entire patchpoint region:
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp72 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) && in AArch64RegisterBankInfo()
78 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) && in AArch64RegisterBankInfo()
80 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) && in AArch64RegisterBankInfo()
85 assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) && in AArch64RegisterBankInfo()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dselect-blsi.mir8 # This test covers the case when OtherInsnID and OtherOpIdx are different in a
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/bugprone/
H A Dshared-ptr-array-mismatch.rst33 This check partially covers the CERT C++ Coding Standard rule

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