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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dpr46877.ll206 %81 = fsub reassoc nsz contract float %0, %1
207 %82 = fmul reassoc nsz contract float %1, %2
208 %83 = fmul reassoc nsz contract float %3, %82
209 %84 = fsub reassoc nsz contract float %0, %83
210 %85 = fmul reassoc nsz contract float %84, %4
211 %86 = fmul reassoc nsz contract float %81, %5
212 %87 = fsub reassoc nsz contract float %0, %86
214 %89 = fmul reassoc nsz contract float %81, %6
215 %90 = fmul reassoc nsz contract float %89, %7
216 %91 = fsub reassoc nsz contract float %0, %90
[all …]
H A Dpow.75.ll30 ; CHECK: Combining: {{.*}}: v4f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], {{.…
31 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v4f32 = fsqrt nnan ninf nsz arcp contract afn re…
32 ; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v4f32 = fsqrt nnan ninf nsz arcp contract af…
33 ; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v4f32 = fmul nnan ninf nsz arcp contract afn reasso…
34 ; CHECK-NEXT: ... into: [[R]]: v4f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQ…
40 ; CHECK: Combining: {{.*}}: v2f64 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], {{.…
41 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v2f64 = fsqrt nnan ninf nsz arcp contract afn re…
42 ; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v2f64 = fsqrt nnan ninf nsz arcp contract af…
43 ; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v2f64 = fmul nnan ninf nsz arcp contract afn reasso…
44 ; CHECK-NEXT: ... into: [[R]]: v2f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQ…
H A Dsqrt-fastmath-mir.ll99 …; CHECK: [[VRSQRTSSr:%[0-9]+]]:fr32 = nnan ninf nsz arcp contract afn reassoc VRSQRTSSr killed […
100 …; CHECK: %3:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr [[COPY]], [[VRSQR…
105 …; CHECK: %8:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %7, killed…
106 …; CHECK: %9:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr [[COPY]], %8, imp…
108 …; CHECK: %11:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %8, [[VMOVSSrm_a…
109 …; CHECK: %12:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %11, kill…
123 …; CHECK: [[VRSQRTSSr:%[0-9]+]]:fr32 = nnan ninf nsz arcp contract afn reassoc VRSQRTSSr killed […
124 …; CHECK: %3:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr [[COPY]], [[VRSQR…
129 …; CHECK: %8:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %7, killed…
130 …; CHECK: %9:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr [[COPY]], %8, imp…
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfma-precision.ll14 %mul = fmul contract reassoc double %b, %a
15 %mul1 = fmul contract reassoc double %d, %c
31 %mul = fmul contract reassoc double %b, %a
32 %mul1 = fmul contract reassoc double %d, %c
47 %mul = fmul contract reassoc double %b, %a
48 %mul1 = fmul contract reassoc double %d, %c
63 %mul = fmul contract reassoc double %b, %a
80 %mul = fmul contract reassoc double %b, %a
111 %ab = fmul contract reassoc double %a, %b
112 %cd = fmul contract reassoc double %c, %d
[all …]
H A Dmachine-combiner.ll211 %7 = fmul contract reassoc nsz double %3, %2
212 %8 = fmul contract reassoc nsz double %5, %4
213 %9 = fadd contract reassoc nsz double %1, %0
226 %7 = fmul contract reassoc nsz float %3, %2
227 %8 = fmul contract reassoc nsz float %5, %4
228 %9 = fadd contract reassoc nsz float %1, %0
229 %10 = fadd contract reassoc nsz float %9, %7
285 %18 = fmul contract reassoc nsz float %2, %1
287 %20 = fmul contract reassoc nsz float %4, %3
289 %22 = fmul contract reassoc nsz float %6, %5
[all …]
H A Dfma-negate.ll20 %0 = fmul contract reassoc double %b, %c
21 %1 = fsub contract reassoc double %a, %0
39 %0 = fmul contract reassoc double %a, %b
40 %1 = fmul contract reassoc double %c, %d
41 %2 = fsub contract reassoc double %0, %1
59 %0 = fsub contract reassoc double -0.0, %a
78 %0 = fmul contract reassoc float %b, %c
79 %1 = fsub contract reassoc float %a, %0
97 %0 = fmul contract reassoc float %a, %b
98 %1 = fmul contract reassoc float %c, %d
[all …]
H A Dfma-aggr-FMF.ll12 %mul1 = fmul contract float %f1, %f2
13 %mul2 = fmul contract float %f3, %f4
14 %add = fadd contract float %mul1, %mul2
19 ; There is no contract on the mul with no extra use so we can't fuse that.
30 %mul1 = fmul contract float %f1, %f2
32 %add = fadd contract float %mul1, %mul2
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fp-combine.ll9 %mul = fmul contract <vscale x 8 x half> %m1, %m2
10 %add = fadd contract <vscale x 8 x half> %acc, %mul
20 %mul = fmul contract <vscale x 4 x half> %m1, %m2
21 %add = fadd contract <vscale x 4 x half> %acc, %mul
31 %mul = fmul contract <vscale x 2 x half> %m1, %m2
32 %add = fadd contract <vscale x 2 x half> %acc, %mul
42 %mul = fmul contract <vscale x 4 x float> %m1, %m2
75 %mul = fmul contract <vscale x 8 x half> %m1, %m2
625 %res = fneg contract <vscale x 8 x half> %add
638 %res = fneg contract <vscale x 4 x half> %add
[all …]
H A Dneon-fma-FMF.ll7 %tmp1 = fmul contract <2 x float> %A, %B;
8 %tmp2 = fadd contract <2 x float> %C, %tmp1;
13 ; the contract on the fadd
18 %tmp2 = fadd contract <2 x float> %C, %tmp1;
26 %tmp1 = fmul contract <2 x float> %A, %B;
34 %tmp1 = fmul contract <2 x float> %A, %B;
35 %tmp2 = fsub contract <2 x float> %C, %tmp1;
40 ; the contract on the fsub
45 %tmp2 = fsub contract <2 x float> %C, %tmp1;
53 %tmp1 = fmul contract <2 x float> %A, %B;
[all …]
H A Dmachine-combiner-instr-fmf.mir48 # CHECK-NEXT: :fpr32 = contract FMADDSrrr [[B]], [[A]], [[C]]
75 %3:fpr32 = contract FMULSrr %1, %0
76 %4:fpr32 = contract FADDSrr killed %3, %2
115 %3:fpr32 = contract FMULSrr %1, %0
128 # CHECK-NEXT: :fpr32 = contract FMADDSrrr [[B]], [[A]], [[C]]
156 %4:fpr32 = contract FADDSrr killed %3, %2
248 # CHECK-NEXT: fpr128 = contract FMLAv2f64 [[C]], [[B]], [[A]]
274 %3:fpr128 = contract FMULv2f64 %1, %0
275 %4:fpr128 = contract FADDv2f64 killed %3, %2
314 %3:fpr128 = contract FMULv2f64 %1, %0
[all …]
H A Dsve-fixed-length-fp-fma.ll19 %mul = fmul contract <4 x half> %op1, %op2
20 %res = fadd contract <4 x half> %mul, %op3
31 %mul = fmul contract <8 x half> %op1, %op2
32 %res = fadd contract <8 x half> %mul, %op3
49 %mul = fmul contract <16 x half> %op1, %op2
50 %res = fadd contract <16 x half> %mul, %op3
84 %mul = fmul contract <32 x half> %op1, %op2
85 %res = fadd contract <32 x half> %mul, %op3
103 %mul = fmul contract <64 x half> %op1, %op2
104 %res = fadd contract <64 x half> %mul, %op3
[all …]
H A Dpow.75.ll30 ; CHECK: Combining: {{.*}}: v4f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], {{.…
31 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v4f32 = fsqrt nnan ninf nsz arcp contract afn re…
32 ; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v4f32 = fsqrt nnan ninf nsz arcp contract af…
33 ; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v4f32 = fmul nnan ninf nsz arcp contract afn reasso…
34 ; CHECK-NEXT: ... into: [[R]]: v4f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQ…
40 ; CHECK: Combining: {{.*}}: v2f64 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], {{.…
41 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v2f64 = fsqrt nnan ninf nsz arcp contract afn re…
42 ; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v2f64 = fsqrt nnan ninf nsz arcp contract af…
43 ; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v2f64 = fmul nnan ninf nsz arcp contract afn reasso…
44 ; CHECK-NEXT: ... into: [[R]]: v2f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQ…
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dpow.75.ll33 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reas…
36 ; CHECK-NEXT: ... into: [[R]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRT…
38 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reas…
41 ; CHECK-NEXT: ... into: [[R]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRT…
43 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reas…
46 ; CHECK-NEXT: ... into: [[R]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRT…
48 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reas…
51 ; CHECK-NEXT: ... into: [[R]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRT…
59 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f64 = fsqrt nnan ninf nsz arcp contract afn reas…
62 ; CHECK-NEXT: ... into: [[R]]: f64 = fmul nnan ninf nsz arcp contract afn reassoc t16, t17
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Ddagcombine-fma-fmad.ll103 %19 = fmul reassoc nnan nsz arcp contract afn float %18, %.i2363
112 %24 = fsub reassoc nnan nsz arcp contract afn float %21, %23
113 %25 = fmul reassoc nnan nsz arcp contract afn float %.i1408, %24
114 %26 = fadd reassoc nnan nsz arcp contract afn float %25, %23
117 %29 = fsub reassoc nnan nsz arcp contract afn float %28, %26
118 %30 = fmul reassoc nnan nsz arcp contract afn float %6, %29
119 %31 = fadd reassoc nnan nsz arcp contract afn float %26, %30
123 %35 = fmul reassoc nnan nsz arcp contract afn float %18, %34
125 %37 = fsub reassoc nnan nsz arcp contract afn float %31, %36
126 %38 = fmul reassoc nnan nsz arcp contract afn float %37, %4
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dfp-contract-fast-pragma.cpp8 #pragma clang fp contract(fast) in fp_contract_1()
18 #pragma clang fp contract(fast) in fp_contract_2()
29 #pragma clang fp contract(fast) in template_muladd()
43 #pragma clang fp contract(fast) in method()
54 #pragma clang fp contract(fast)
63 #pragma clang fp contract(fast) contract(off)
H A Dfp-contract-on-pragma.cpp7 #pragma clang fp contract(on) in fp_contract_1()
17 #pragma clang fp contract(on) in fp_contract_2()
28 #pragma clang fp contract(on) in template_muladd()
41 #pragma clang fp contract(on) in method()
51 #pragma clang fp contract(on)
58 #pragma clang fp contract(off)
74 #pragma clang fp contract(on) in fp_contract_7()
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AMDGPU/
H A Dfused_costs.ll79 %f32c = fmul contract float undef, undef
80 %f32cadd = fadd contract float %f32c, undef
88 %f32c_2 = fmul contract float undef, undef
89 %f32csub = fsub contract float %f32c_2, undef
160 %f16c = fmul contract half undef, undef
161 %f15cadd = fadd contract half %f16c, undef
169 %f16c_2 = fmul contract half undef, undef
170 %f15csub = fsub contract half %f16c_2, undef
241 %f64c = fmul contract double undef, undef
242 %f64cadd = fadd contract double %f64c, undef
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dreorder-reused-masked-gather.ll26 %9 = fadd reassoc nsz arcp contract afn float %8, 0.000000e+00
29 %11 = fadd reassoc nsz arcp contract afn float %4, 0.000000e+00
32 %13 = fadd reassoc nsz arcp contract afn float %6, 0.000000e+00
35 %15 = fadd reassoc nsz arcp contract afn float %8, 0.000000e+00
38 %17 = fadd reassoc nsz arcp contract afn float %4, 0.000000e+00
42 %20 = fadd reassoc nsz arcp contract afn float %6, 0.000000e+00
45 %22 = fadd reassoc nsz arcp contract afn float %8, 0.000000e+00
49 %25 = fadd reassoc nsz arcp contract afn float %4, %18
52 %27 = fadd reassoc nsz arcp contract afn float %6, 0.000000e+00
55 %29 = fadd reassoc nsz arcp contract afn float %8, %23
[all …]
/llvm-project-15.0.7/mlir/test/Integration/Dialect/Vector/CPU/
H A Dtest-contraction.mlir202 %dp1 = vector.contract #dotp_trait %a, %b, %f0
204 %dp2 = vector.contract #dotp_trait %a, %b, %f1
216 %mv1 = vector.contract #matvec_trait %A, %c, %z1
218 %mv2 = vector.contract #matvec_trait %A, %c, %a
232 %mv4 = vector.contract #mattransvec_trait %A, %c, %a
244 %mm1 = vector.contract #matmat_trait %A, %B, %z2
246 %mm2 = vector.contract #matmat_trait %A, %B, %A
334 %mm11 = vector.contract #matmat_trait %C, %D, %z3
336 %mm12 = vector.contract #matmat_trait %C, %D, %mm11
345 %c1 = vector.contract #contract2d_trait %A, %B, %f0
[all …]
/llvm-project-15.0.7/clang/test/Parser/
H A Dpragma-fp.cpp20 #pragma clang fp contract on in test_3()
28 #pragma clang fp contract(while) in test_4()
36 #pragma clang fp contract(maybe) in test_5()
44 #pragma clang fp contract(fast in test_6()
52 #pragma clang fp contract(fast) * in test_7()
62 #pragma clang fp contract(fast) in test_8()
73 #pragma clang fp exceptions(maytrap) contract(fast) reassociate(on) in test_10()
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-unroll-options.mlir7 %0 = vector.contract
157 %0 = vector.contract
166 // CHECK: vector.contract {
168 // CHECK: vector.contract {
170 // CHECK: vector.contract {
172 // CHECK: vector.contract {
174 // CHECK: vector.contract {
176 // CHECK: vector.contract {
178 // CHECK: vector.contract {
180 // CHECK: vector.contract {
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dfp-mul-14.ll9 %i = fmul contract float %arg, 0xBE6777A5C0000000
10 %i4 = fadd contract float %i, 1.000000e+00
11 %i5 = fmul contract float %arg, 0xBE6777A5C0000000
12 %i6 = fadd contract float %i5, 1.000000e+00
13 %i7 = fmul contract float %i4, 2.000000e+00
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/X86/
H A Dfastmath.mir21 ; CHECK: %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
22 %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
27 ; CHECK: %8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
28 %8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
29 ; CHECK: %9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
30 %9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
H A Dmircanon-flags.mir19 ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = contract VMULSSrr
22 ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nsz arcp contract afn reassoc VMULSSrr
23 ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = contract afn reassoc VMULSSrr
30 %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
33 %8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
34 %9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
/llvm-project-15.0.7/llvm/test/Transforms/LowerMatrixIntrinsics/
H A Dmultiply-fused.ll59 ; CHECK-NEXT: [[TMP12:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]]
63 ; CHECK-NEXT: [[TMP14:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT21]]
103 ; CHECK-NEXT: [[TMP23:%.*]] = fmul contract <2 x double> [[COL_LOAD57]], [[SPLAT_SPLAT69]]
107 ; CHECK-NEXT: [[TMP25:%.*]] = fmul contract <2 x double> [[COL_LOAD57]], [[SPLAT_SPLAT75]]
148 ; CHECK-NEXT: [[TMP35:%.*]] = fmul contract <2 x double> [[COL_LOAD111]], [[SPLAT_SPLAT123]]
152 ; CHECK-NEXT: [[TMP37:%.*]] = fmul contract <2 x double> [[COL_LOAD111]], [[SPLAT_SPLAT129]]
194 ; CHECK-NEXT: [[TMP48:%.*]] = fmul contract <2 x double> [[COL_LOAD165]], [[SPLAT_SPLAT177]]
286 ; CHECK-NEXT: [[TMP0:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]]
290 ; CHECK-NEXT: [[TMP2:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT14]]
330 ; CHECK-NEXT: [[TMP11:%.*]] = fmul contract <2 x double> [[COL_LOAD50]], [[SPLAT_SPLAT62]]
[all …]

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