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Searched refs:cinv (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dthumbv8.1m.s1075 # CHECK: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
1076 # CHECK-FP: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
1077 # CHECK-NOLOB: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
1078 cinv lr, r12, hs label
1110 # CHECK: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
1111 # CHECK-FP: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
1112 # CHECK-NOLOB: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
H A Dmve-scalar-shift.s58 # CHECK: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
59 # CHECK-NOMVE: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
60 cinv lr, r12, hs label
86 # CHECK: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
87 # CHECK-NOMVE: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dthumbv8.1m.s11 # CHECK: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
32 # CHECK: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
H A Dthumb2-v8.1m.txt1124 # CHECK: cinv lr, r12, hs @ encoding: [0x5c,0xea,0x3c,0xae]
1145 # CHECK: cinv lr, r2, pl @ encoding: [0x52,0xea,0x42,0xae]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dcsel.ll47 ; CHECK-NEXT: cinv r0, r1, gt
60 ; CHECK-NEXT: cinv r0, r1, le
152 %cinv = xor i32 %c, -1
153 %spec.select = select i1 %cmp, i32 %b, i32 %cinv
330 ; CHECK-NEXT: cinv r0, r0, gt
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-csel.ll40 ; CHECK-NEXT: cinv w8, w0, ne
142 ; CHECK-NEXT: cinv w0, w8, eq
155 ; CHECK-NEXT: cinv x0, x8, eq
H A Dsshl_sat.ll150 ; CHECK-NEXT: cinv w10, w10, ge
H A Dselect_const.ll340 ; CHECK-NEXT: cinv w0, w8, eq
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dbasic-a64-diagnostics.s1428 cinv w3, wsp, ne
1429 cinv sp, x9, eq
1430 cinv w8, x7, nv
H A Dbasic-a64-instructions.s1425 cinv w3, w5, gt
1426 cinv wzr, w4, le
1427 cinv w9, wzr, lt
1432 cinv x3, x5, gt
1433 cinv xzr, x4, le
1434 cinv x9, xzr, lt
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Neoverse/
H A DN2-basic-instructions.s428 cinv w3, w5, gt label
429 cinv wzr, w4, le label
431 cinv x3, x5, gt label
432 cinv xzr, x4, le label
1760 # CHECK-NEXT: 1 1 0.25 cinv w3, w5, gt
1761 # CHECK-NEXT: 1 1 0.25 cinv wzr, w4, le
1763 # CHECK-NEXT: 1 1 0.25 cinv x3, x5, gt
1764 # CHECK-NEXT: 1 1 0.25 cinv xzr, x4, le
2944 … - - - - - - 0.25 0.25 0.25 0.25 - - cinv w3, w5, gt
2945 …- - - - - - 0.25 0.25 0.25 0.25 - - cinv wzr, w4, le
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Cortex/
H A DA55-basic-instructions.s428 cinv w3, w5, gt label
429 cinv wzr, w4, le label
431 cinv x3, x5, gt label
432 cinv xzr, x4, le label
1760 # CHECK-NEXT: 1 3 0.50 cinv w3, w5, gt
1761 # CHECK-NEXT: 1 3 0.50 cinv wzr, w4, le
1763 # CHECK-NEXT: 1 3 0.50 cinv x3, x5, gt
1764 # CHECK-NEXT: 1 3 0.50 cinv xzr, x4, le
2943 …0.50 0.50 - - - - - - - - - - cinv w3, w5, gt
2944 ….50 0.50 - - - - - - - - - - cinv wzr, w4, le
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Dbasic-a64-instructions.txt981 # CHECK: cinv w3, w5, gt
982 # CHECK: cinv wzr, w4, le
984 # CHECK: cinv x3, x5, gt
985 # CHECK: cinv xzr, x4, le
987 # "cinv x1, x0, nv" and "cinv w9, w8, al" are invalid aliases for these two
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td2373 def : InstAlias<"cinv $dst, $src, $cc",
2375 def : InstAlias<"cinv $dst, $src, $cc",
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td5669 def : InstAlias<"cinv\t$Rd, $Rn, $fcond",