Home
last modified time | relevance | path

Searched refs:cfcmsa (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/Mips/msa/
H A Dtest_ctrlregs.s37 cfcmsa $1, $msair label
38 cfcmsa $1, $0 label
39 cfcmsa $2, $msacsr label
40 cfcmsa $2, $1 label
42 cfcmsa $3, $2 label
44 cfcmsa $4, $3 label
46 cfcmsa $5, $4 label
48 cfcmsa $6, $5 label
49 cfcmsa $7, $msamap label
50 cfcmsa $7, $6 label
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/msa/
H A Dtest_ctrlregs.txt3 0x78 0x7e 0x00 0x59 # CHECK: cfcmsa $1, $0
4 0x78 0x7e 0x00 0x59 # CHECK: cfcmsa $1, $0
5 0x78 0x7e 0x08 0x99 # CHECK: cfcmsa $2, $1
6 0x78 0x7e 0x08 0x99 # CHECK: cfcmsa $2, $1
7 0x78 0x7e 0x10 0xd9 # CHECK: cfcmsa $3, $2
8 0x78 0x7e 0x10 0xd9 # CHECK: cfcmsa $3, $2
9 0x78 0x7e 0x19 0x19 # CHECK: cfcmsa $4, $3
10 0x78 0x7e 0x19 0x19 # CHECK: cfcmsa $4, $3
11 0x78 0x7e 0x21 0x59 # CHECK: cfcmsa $5, $4
12 0x78 0x7e 0x21 0x59 # CHECK: cfcmsa $5, $4
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Delm_cxcmsa.ll9 %0 = tail call i32 @llvm.mips.cfcmsa(i32 0)
14 ; CHECK: cfcmsa $[[R1:[0-9]+]], $0
19 %0 = tail call i32 @llvm.mips.cfcmsa(i32 1)
24 ; CHECK: cfcmsa $[[R1:[0-9]+]], $1
34 ; CHECK: cfcmsa $[[R1:[0-9]+]], $2
44 ; CHECK: cfcmsa $[[R1:[0-9]+]], $3
54 ; CHECK: cfcmsa $[[R1:[0-9]+]], $4
64 ; CHECK: cfcmsa $[[R1:[0-9]+]], $5
74 ; CHECK: cfcmsa $[[R1:[0-9]+]], $6
84 ; CHECK: cfcmsa $[[R1:[0-9]+]], $7
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td262 // These registers do not exist, but instructions like `cfcmsa`
H A DMipsScheduleP5600.td311 // bnz.[bhwdv], cfcmsa, ctcmsa
H A DMipsScheduleGeneric.td1461 // bnz.[bhwdv], cfcmsa, ctcmsa
H A DMipsMSAInstrInfo.td1805 string AsmString = "cfcmsa\t$rd, $cs";