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Searched refs:cacheline (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dr600.func-alignment.ll5 ; Functions need to be cacheline (256B) aligned to prevent GPU hangs
/llvm-project-15.0.7/openmp/runtime/src/
H A Dkmp_wait_release.h723 void *cacheline = (void *)(kmp_uintptr_t(spin) & ~(CACHE_LINE - 1));
737 __kmp_umonitor(cacheline);
741 __kmp_mm_monitor(cacheline, 0, 0);
H A Dkmp.h1349 static inline void __kmp_umonitor(void *cacheline) { in __kmp_umonitor() argument
1353 : "a"(cacheline) in __kmp_umonitor()
1356 _umonitor(cacheline); in __kmp_umonitor()
1388 __kmp_mm_monitor(void *cacheline, unsigned extensions, unsigned hints) { in __kmp_mm_monitor() argument
1389 _mm_monitor(cacheline, extensions, hints); in __kmp_mm_monitor()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DREADME.txt351 Make sure the instruction which starts a loop does not cross a cacheline
355 In the new trace, the hot loop has an instruction which crosses a cacheline
358 to grab the bytes from the next cacheline.