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Searched refs:cachee (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/Mips/eva/
H A Dvalid_R6.s7 … cachee 31, 255($7) # CHECK: cachee 31, 255($7) # encoding: [0x7c,0xff,0x7f,0x9b]
8 … cachee 0, -256($4) # CHECK: cachee 0, -256($4) # encoding: [0x7c,0x80,0x80,0x1b]
9 … cachee 5, -140($4) # CHECK: cachee 5, -140($4) # encoding: [0x7c,0x85,0xba,0x1b]
H A Dvalid_preR6.s11 … cachee 31, 255($7) # CHECK: cachee 31, 255($7) # encoding: [0x7c,0xff,0x7f,0x9b]
12 … cachee 0, -256($4) # CHECK: cachee 0, -256($4) # encoding: [0x7c,0x80,0x80,0x1b]
13 … cachee 5, -140($4) # CHECK: cachee 5, -140($4) # encoding: [0x7c,0x85,0xba,0x1b]
H A Dinvalid.s8 cachee -1, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
9 cachee 32, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
H A Dinvalid-noeva-wrong-error.s22 … cachee 31, 255($7) # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
23 … cachee 0, -256($4) # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
24 … cachee 5, -140($4) # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/eva/
H A Dvalid_R6-eva.txt4 0x7c 0xff 0x7f 0x9b # CHECK: cachee 31, 255($7)
5 0x7c 0x80 0x80 0x1b # CHECK: cachee 0, -256($4)
6 0x7c 0x85 0xba 0x1b # CHECK: cachee 5, -140($4)
H A Dvalid_preR6-eva.txt8 0x7c 0xff 0x7f 0x9b # CHECK: cachee 31, 255($7)
9 0x7c 0x80 0x80 0x1b # CHECK: cachee 0, -256($4)
10 0x7c 0x85 0xba 0x1b # CHECK: cachee 5, -140($4)
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmicromips32r6-eva.s14 # CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6]
41 # CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
65 cachee 1, 8($5)
H A Dmicromips-eva.s14 # CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6]
49 # CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
81 cachee 1, 8($5)
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips/
H A Dinvalid.s19 cachee 0, -513($7) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
20 cachee 0, 512($7) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
H A Dvalid.s285 cachee 1, 8($5) # CHECK: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08] label
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsEVAInstrInfo.td175 class CACHEE_DESC : CACHEE_DESC_BASE<"cachee", mem_simm9, II_CACHEE>;
H A DMicroMipsInstrInfo.td1075 def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>,
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dmicromips-eva.mir213 # CHECK: 60 41 a6 05 cachee 2, 5($1)
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/micromips32r3/
H A Dvalid-el.txt191 0x25 0x60 0x08 0xa6 # CHECK: cachee 1, 8($5)
H A Dvalid.txt191 0x60 0x25 0xa6 0x08 # CHECK: cachee 1, 8($5)
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/micromips32r6/
H A Dvalid.txt211 0x60 0x25 0xa6 0x08 # CHECK: cachee 1, 8($5)