Searched refs:buildSExtInReg (Results 1 – 6 of 6) sorted by relevance
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 193 Builder.buildSExtInReg(DstReg, TruncSrc, SizeInBits); in tryCombineSExt()
|
| H A D | MachineIRBuilder.h | 646 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) { in buildSExtInReg() function
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1087 B.buildSExtInReg(MI.getOperand(0), WideLoad, MemSize); in applyMappingLoad()
1733 auto ExtLo = B.buildSExtInReg(S32, Bitcast, 16); in unpackV2S16ToS32()
2454 B.buildSExtInReg(DstRegs[0], SrcRegs[0], Amt); in applyMappingImpl()
2461 B.buildSExtInReg(DstRegs[1], DstRegs[0], Amt - 32); in applyMappingImpl()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 483 return buildSExtInReg(Res, Op, 1); in buildBoolExtInReg()
|
| H A D | LegalizerHelper.cpp | 2002 ExtResult = MIRBuilder.buildSExtInReg(WideTy, Mul, SrcBitWidth); in widenScalarMulo()
2960 MIRBuilder.buildSExtInReg(LoadReg, NewLoad, MemSizeInBits); in lowerLoad()
7239 MaskElt = MIRBuilder.buildSExtInReg(MaskTy, MaskElt, 1).getReg(0); in lowerSelect()
|
| H A D | CombinerHelper.cpp | 2762 Builder.buildSExtInReg(MI.getOperand(0).getReg(), Src, Size - ShiftAmt); in applyAshShlToSextInreg()
|